EE 243. Advanced IC Processing and Layout
This course emphasizes the physical principles and models used in IC fabrication technology. It starts with an overview of the CMOS fabrication sequence, its key technology modules, and the issues that limit these processes. We then cover the front-end of the line (FEOL) processes: mechanisms and models for implantation, oxidation, and diffusion. We will discuss advanced models for optical image formation and resolution enhancement, resist response, defect printability, inspection and next generation nm-scale printing. Back end of the line (BEOL) processes include etching, physical depositions (sputtering) and chemical deposition (ALD and Epi), CMP, multilevel metallization, and heterogeneous integration. Contemporary issues such as high-k dielectric and strain engineering will be use as case studies of the modules. Extension of these process modules for flat panel displays, MEMS, Photovoltaics, and Nanotechnology will be discussed. The last 3 weeks cover basic statistical process control (SPC) and design of experiments (DOE) as used to support high yield manufacturing.