Faculty Publications - Robert K. Brayton

Books

  • F. Mo and R. K. Brayton, Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design, Boston: Kluwer Academic Publishers, 2004. [abstract]
  • S. P. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Cross-Talk Noise Immune VLSI Design using Regular Layout Fabrics, Boston: Kluwer Academic, 2001. [abstract]
  • T. Kam, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Functional Optimization, Boston, MA: Kluwer Academic Publishers, 1997. [abstract]
  • T. Villa, T. Kam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Synthesis of Finite State Machines: Logic Optimization, Boston: Kluwer Academic, 1997. [abstract]
  • R. Murgai, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Logic Synthesis for Field-Programmable Gate Arrays, The Kluwer International Series in Engineering and Computer Science; SECS 324, Boston: Kluwer Academic Publishers, 1995. [abstract]
  • W. K. C. Lam and R. K. Brayton, Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis, The Kluwer International Series in Engineering and Computer Science; SECS 270. VLSI, Computer Architecture and Digital Signal Processing, Boston: Kluwer Academic Publishers, 1994. [abstract]
  • P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications, The Kluwer International Series in Engineering and Computer Science; SECS 139, Boston: Kluwer Academic, 1991. [abstract]
  • R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, The Kluwer International Series in Engineering and Computer Science, Vol. 2, Boston, MA: Kluwer Academic Publishers, 1984. [abstract]
  • R. K. Brayton and R. Spence, Sensitivity and Optimization, Computer-Aided Design of Electronic Circuits; v. 2, Amsterdam: Elsevier Scientific, 1980. [abstract]

Book chapters or sections

  • J. R. Jiang and R. K. Brayton, "Functional dependency for verification reduction," in Computer Aided Verification: Proc. 16th Intl. Conf. (CAV 2004), R. Alur and D. A. Peled, Eds., Lecture Notes in Computer Science, Vol. 3114, Berlin, Germany: Springer-Verlag, 2004, pp. 268-280.

Articles in journals or magazines

Articles in conference proceedings

  • K. Aadithya, S. Ray, P. Nuzzo, A. Mishchenko, R. K. Brayton, and J. Roychowdhury, "ABCD-NL: Approximating Continuous Non-Linear Dynamical Systems using Purely Boolean Models for Analog/Mixed-Signal Verification," in Proc. IEEE Asia South-Pacific Design Automation Conference, 2014.
  • M. Case, A. Mishchenko, and R. K. Brayton, "Cut-based inductive invariant computation," in Proc. 17th Intl. Workshop on Logic and Synthesis (IWLS 2008), New York, NY: The Association for Computing Machinery, Inc., 2008.
  • A. Mishchenko and R. K. Brayton, "Recording synthesis history for sequential verification," in Proc. 17th Intl. Workshop on Logic and Synthesis (IWLS 2008), New York, NY: The Association for Computing Machinery, Inc., 2008.
  • A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks," in Proc. 17th Intl. Workshop on Logic and Synthesis (IWLS 2008), New York, NY: The Association for Computing Machinery, Inc., 2008.
  • A. Mishchenko, M. Case, R. K. Brayton, and S. Jang, "Scalable and scalably-verifiable sequential synthesis," in Proc. 17th Intl. Workshop on Logic and Synthesis (IWLS 2008), New York, NY: The Association for Computing Machinery, Inc., 2008.
  • A. Mishchenko, R. K. Brayton, and S. Jang, "Global delay optimization using structural choices," in Proc. 17th Intl. Workshop on Logic and Synthesis (IWLS 2008), New York, NY: The Association for Computing Machinery, Inc., 2008.
  • A. P. Hurst, A. Mishchenko, and R. K. Brayton, "Scalable min-register retiming under timing and initializability constraints," in Proc. 45th ACM/IEEE Annual Design Automation Conf. (DAC 2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 534-539.
  • M. L. Case, V. N. Kravets, A. Mishchenko, and R. K. Brayton, "Merging nodes under sequential observability," in Proc. 45th ACM/IEEE Annual Design Automation Conf. (DAC 2008), New York, NY: The Association for Computing Machinery, Inc., 2008, pp. 540-545.
  • A. Mishchenko, S. Cho, S. Chatterjee, and R. K. Brayton, "Combinational and sequential mapping with priority cuts," in 2007 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD '07) Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2007, pp. 354-361.
  • F. Mo and R. K. Brayton, "A simultaneous bus orientation and bused pin flipping algorithm," in 2007 IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD '07) Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2007, pp. 386-389.
  • M. L. Case, A. Mischenko, and R. K. Brayton, "Automated extraction of inductive invariants to aid model checking," in Proc. 2007 Formal Methods in Computer Aided Design, Los Alamitos, CA: IEEE Computer Society, 2007, pp. 165-172.
  • A. P. Hurst, A. Mishchenko, and R. K. Brayton, "Fast minimum-register retiming via binary maximum-flow," in Proc. 2007 Formal Methods in Computer-Aided Design (FMCAD '07), Los Alamitos, CA: IEEE Computer Society, 2007, pp. 181-187.
  • A. Mishchenko, R. K. Brayton, J. H. Jiang, and S. Jan, "SAT-based logic optimization and resynthesis," in Proc. 16th Intl. Workshop on Logic and Synthesis, New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 358-364.
  • S. Chatterjee, Z. Wei, A. Mishchenko, and R. K. Brayton, "A linear time algorithm for optimum tree placement," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 336-342.
  • A. Hurst, A. Mishchenko, and R. K. Brayton, "Fast minimum-register retiming via binary maximum-flow," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 328-335.
  • M. L. Case, A. Mishchenko, and R. K. Brayton, "Automated extraction of inductive invariants to aid model checking," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 282-289.
  • J. Pistorius, M. Hutton, A. Mishchenko, and R. K. Brayton, "Benchmarking method and designs targeting logic synthesis for FPGAs," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 230-237.
  • A. Mishchenko, S. Cho, S. Chatterjee, and R. K. Brayton, "Combinational and sequential mapping with priority cuts," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 91-98.
  • A. Hurst, A. Mishchenko, and R. K. Brayton, "Minimizing implementation costs with end-to-end retiming," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 9-16.
  • R. K. Brayton and A. Mishchenko, "Sequential rewriting and synthesis," in Proc. 16th Intl. Workshop on Logic and Synthesis (IWLS 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 1-8.
  • S. Chatterjee, A. Mishchenko, R. K. Brayton, and A. Kuehlmann, "On resolution proofs for combinational equivalence," in Proc. 44th Annual ACM/IEEE Design Automation Conf. (DAC 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 600-605.
  • F. Mo and R. K. Brayton, "Semi-detailed bus routing with variation reduction," in Proc. 2007 Intl. Symp. on Physical Design (ISPD '07), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 143-150.
  • T. Villa, S. Zharikova, N. Yevtushenko, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "A new algorithm for the largest compositionally progressive solution of synchronous language equations," in Proc. 17th ACM Great Lakes Symp. on VLSI (GLSVLSI 2007), New York, NY: The Association for Computing Machinery, Inc., 2007, pp. 441-444.
  • Y. S. Yang, S. Sinha, A. Veneris, and R. K. Brayton, "Automating logic rectification by approximate SPFDs," in Proc. 2007 Asia and South Pacific Design Automation Conf. (ASP-DAC '07), Piscataway, NJ: IEEE Press, 2007, pp. 402-407.
  • A. Mishchenko, S. Chatterjee, and R. K. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis," in Proc. IEEE/ACM 43rd Annual Conf. on Design Automation, New York, NY: ACM Press, 2006, pp. 532-535.
  • Y. Li, A. Kondratyev, and R. K. Brayton, "Gaining predictability and noise immunity in global interconnects," in Proc. 5th Intl. Conf. on Application of Concurrency to System Design, Los Alamitos, CA: IEEE Computer Society, 2005, pp. 176-185.
  • A. Mishchenko and R. K. Brayton, "SAT-based complete don't-care computation for network optimization," in Proc. Design, Automation and Test in Europe, Vol. 1, Los Alamitos, CA: IEEE Computer Society, 2005, pp. 412-417.
  • F. Mo and R. K. Brayton, "A timing-driven module-based chip design flow," in Proc. 2004 41st Design Automation Conf., New York, NY: ACM Press, 2004, pp. 67-70.
  • Y. Jiang, S. Matic, and R. K. Brayton, "Generalized cofactoring for logic function evaluation," in Proc. 2003 40th Design Automation Conf., Piscataway, NJ: IEEE Press, 2003, pp. 155-158.
  • N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko, and A. L. Sangiovanni-Vincentelli, "Equisolvability of series vs. controller's topology in synchronous language equations," in Proc. 6th Design, Automation and Test in Europe Conf. and Exhibition (DATE 2003), N. Wehn and D. Verkest, Eds., Los Alamitos, CA: IEEE Computer Society, 2003, pp. 1154-1155.
  • M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "HW/SW Partitioning and Code Generation of Embedded Control Applica- tions on a Reconfigurable Architecture Platform," in Proceedings of the tenth international symposium on Hardware/software codesign, 2002.
  • M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform," in Proc. 10th Intl. Symp. on Hardware/Software Codesign (CODES 2002), New York, NY: ACM Press, 2002, pp. 151-156.
  • R. K. Brayton, "Compatible observability don't cares revisited," in IEEE/ACM Intl. Conf. on Computer Aided Design (ICCAD 2001). Digest of Technical Papers, Piscataway, NJ: IEEE Press, 2001, pp. 618-623.
  • A. Tabbara, R. K. Brayton, and A. R. Newton, "Retiming for DSM with area-delay trade-offs and delay constraints," in Proc. 36th Design Automation Conf. (DAC 1999), New York, NY: ACM, Inc., 1999, pp. 725-730.
  • R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa, "VIS: A system for verification and synthesis," in Lecture Notes in Computer Science: Computer Aided Verification, R. Alur and T. A. Henzinger, Eds., Vol. 1102, London, UK: Springer-Verlag, 1996, pp. 428-432.
  • E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. IEEE 1992 Intl. Conf. on Computer Design: VLSI in Computers and Processors, Los Alamitos, CA: IEEE Computer Society Press, 1992, pp. 328-333.
  • A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "Reduced offsets for two-level multi-valued logic minimization," in Proc. 275h ACM/IEEE Conf. on Design Automation (DAC '90), New York, NY: ACM, Inc., 1990, pp. 290-296.
  • M. Beardslee, C. Kring, R. Murgai, H. Savoj, R. K. Brayton, and A. R. Newton, "SLIP: A software environment for System Level Interactive Partitioning," in 1989 IEEE Intl. Conf. on Computer-Aided Design (ICCAD-89). Digest of Technical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1989, pp. 280-283.
  • A. A. Malik, R. K. Brayton, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A modified approach to two-level logic minimization," in 1988 IEEE Intl. Conf. on Computer-Aided Design (ICCAD-88). Digest of Technical Papers, Los Alamitos, CA: IEEE Computer Society Press, 1988, pp. 106-109.
  • R. K. Brayton, G. D. Hachtel, L. A. Hemachandra, A. R. Newton, and A. L. Sangiovanni-Vincentelli, "A comparison of logic minimization strategies using ESPRESSO: An APL program package for partitioned logic minimalization," in Proc. 1982 IEEE Intl. Symp. on Circuits and Systems (ISCAS-82), New York, NY: IEEE, 1982, pp. 42-48. [abstract]
  • R. K. Brayton and C. McMullen, "The decomposition and factorization of Boolean expressions," in Proc. 1982 IEEE Intl. Symp. on Circuits and Systems, Vol. 1, New York, NY: IEEE Press, 1982, pp. 49-54.

Technical Reports

Patents

Talks or presentations

  • A. Tabbara, R. K. Brayton, and A. R. Newton, "Retiming for DSM with area-delay trade-offs and delay constraints," presented at Intl. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU '99), Monterey, CA, March 1999.