Computer Science 252: Graduate Computer Architecture
University of California
Dept. of Electrical Engineering and Computer Sciences
Announcements | Description
| Organization | Projects
| Schedule (daily) | Handouts
Related | Links
|David E. Culler
Take home exam: PDF format,
Project Presentation Schedule
Monday May 12
Sensor Networks with Base Stations
Participants: Andrej Bogdanov, Elitza Maneva, Samantha Riesenfeld
Dynamic voltage-scaling at link-time, Ben Schwartz
Evaluation of Matrix Operation on Reconfigurable Application Driven
Participants: Chen Chang, Gerald Wang
Project Webpage: http://inst.eecs.berkeley.edu/~chenzh/cs252_project.htm
Simulation of Localization Algorithms, Tye and Long
Aggregation Query Under Uncertainty in Sensor Networks
Participants: Yozo Hida, Paul Huang, Rajesh Nishtala
Project Webpage: http://www.cs.berkeley.edu/~yozo/cs252/project.html
Efficient Broadcasts in Sensor Networks
Participants: Sanjeev Kohli, Vinay Krishnan, Cheng Tien Ee
Project Webpage: http://www.eecs.berkeley.edu/~ct-ee/cs252/
Analysis of Speech Recognition for Low-Cost Hardware
Participants: Sukun Kim, Sergiu Nedevschi, Rabin Patra
Project Webpage: http://www.cs.berkeley.edu/~rkpatra/cs252/
CS grads: the faculty voted to change the Preliminary Breadth Courses
requirements in Fall 2000 to be systems, theory, and systems meets theory:
therefore CS 252 is included with a set of systems courses such as CS262
Graduate survey of contemporary computer organizations covering: early
systems, CPU design, instruction sets, control, processors, busses, ALU,
memory, pipelined computers, multiprocessors, and case studies.
Term paper or project required.Three hours of lecture per week.
152 or equivalent.
Computer architecture is a vibrant and ever changing area; this course
will attempt to convey that to students. It focuses on the
design and implementation of computer systems, as well as techniques for
analyzing and comparing alternative computer organizations. We will
take the broad view of computer architecture as it evolves - not just CPU
design, but the places where hardware and software come together from tiny
embedded devices to massive internet service platforms.
Students will learn about styles of computer implementation and organization
from a historical and modern perspective. Traditional concepts such as
pipelining, instruction-level parallelism, memory hierarchies, and input/output
architectures will be discussed. Further, modern issues such as data speculation,
dynamic compilation, communication architecture, multiprocessors, and VLSI
scaling concerns will be introduced and discussed. Cutting-edge paradigms
such as low-power wireless, network processors, reliability, and scalable
systems will be explored
In addition to the textbook, this course includes a number of readings
from research papers. Such papers are important for a number of reasons,
not the least of which is to understand that design decisions are not always
black and white. Students will also undertake a major computing systems
analysis and design project of their own choosing.
This term I hope to make the class very interactive. We
have a very good text and a solid basis of original papers. Lectures
will be a discussion around issues raised by the readings and a counter-point,
rather than a rehash of the reading material. You must do the reading
assigned in the schedule for each class prior to the class meeting and
bring one question raised by what you have read. Questions will be
collected at the beginning of class and will serve to guide how the lecture
material unfolds and as a starting point for discussion.
20% Class Participation, including discussion questions.
10% Homeworks (work in pairs)
30% Examinations (1 Quiz, 1 Take home)
40% Research Project (work in pairs)
Grading Guidelines for Graduate courses
|| Professor David
627 Soda Hall, 643-7572, email@example.com
Office Hours: Mon 2:30 - 3:30, Wed 11-12, or by appt.
contact Willa Walker, 643-2568,
willa@EECS.Berkeley.EDU, 626 Soda, for appt.
Lecture: M,W 1:00 - 2:30 310 Soda Hall
The class newsgroup is ucb.class.cs252
||J. L. Hennessy and D. A. Patterson, Computer
Architecture: A Quantitative Approach, 3rd Edition, Morgan Kaufmann
Publishing Co., Menlo Park, CA. 2002.
||Readings in Computer Architecture, Mark Hill (Editor), Norman Jouppi
(Editor), Gurindar Sohi (Editor), Morgan Kaufmann Publishing Co., Menlo
Park, CA. 1999
See linked schedule page.
Every effort will be made to get the notes on the web prior to the lecture.
Note, however, that the notes may be updated slightly following the lecture.
for instructions regarding how to view pdf files.
Permission is granted to copy and distribute this material for educational
purposes only, provided that the complete bibliographic citation and following
credit line is included: "Copyright 2002 UCB." Permission is granted to
alter and distribute this material provided that the following credit line
is included: "Adapted from (complete bibliographic citation). Copyright
This material may not be copied or distributed for commercial purposes
without express written permission of the copyright holder. The only exception
is for copies of these lecture notes for course readers from copy companies
like Copymat or Kinkos.
Click here to see a list of suggested projects.
Related Course Pages
Other Useful Links and Resources
Tools: a short story,
by Remzi Arpaci, briefly describes pixie, pixstats, prof, dinero, qpt,
CPROF, spim, Cacti, shade, and spixtools. Most of the specific directories
and files mentioned are on the instructional machines.
Architectural Research Tool Set (WARTS) - including QPT, QPT2, CPROF,
Tycho, dineroIII, and EEL
ATOM - A toolkit that can be used for tracing, and much more. Only runs
on Alphas. Log in to either saidin.eecs (an instructional machine)
or speeding.cs (on the same file system as the NOW machines)
EEL - A toolkit that can be used for tracing, and much more. Only runs
See the following class
project for some more details.
- A tracing tool for Intel x86 platforms running either Win95, WinNT, or
Linux. Courtesy of Harvard University and the University of Washington.
Simulation And Tracing - This contains a huge list of simulators, emulators,
and tracing tools, including an extensive bibliography as well as list
of people to contact
Traces - user level traces of Windows NT applications collected using
Traces - another link.
Monster Traces - Traces of 8 applications (run under Ultrix and Mach) collected
with a hardware monitor on a DEC-MIPS workstation. Includes user and kernel
activity. First presented in a paper
which appeared in ISCA95. Courtesy of Richard Uhlig (thanks to Christoforos
for getting them). More details forthcoming when these are actually available.
Patchwrx - Single-processor portions of traces, containing user and kernel
references, from 2 spec benchmarks and a database, running under Windows
NT on an Alpha. Courtesy of Dick Sites, from DEC. A few projects from last
spring's IRAM class as well as a Spring 1996 CS 252 projects detail some
caveats concerning the accuracy of these traces (and of Dick Sites' conclusions
regarding "Caches Don't Work".)
State Univ Trace Database
Internet Traffic Archive-
contains 5 traces of TCP/ethernet traffic, 6 traces of requests received
by specific web servers, 2 traces of web client requests (from some pool
of clients), and a set of traceroute measurements. Traces can span hours
or weeks and may occupy multiple megabytes uncompressed.
More info from Westley Weimer: "The web requests (the only ones I have
examined in detail) tend to be long text files of tuples: (client-ip, time,
document requested, size, etc) with the exact fields and format varying
by trace. One trace even comes with a C interface for reading their records.
simulator is a very flexible simulation package that comes with a working
version of GCC and precompiled versions of the SPEC 95 benchmark
suite. SimpleScalar comes with several different simulators, each
of which supports a different level of simulation: everything from timing-free
but fast simulation (for debugging), to a full out-of-order simulator.
The simulated processor is a variant of the MIPS architecture.
For a precompiled version that works on Linux X86, see Kubiatowicz's
home page: ~kubitron/simplescalar.
The CPU Info
Center has a good summary of high-level info
MIPS does a very good job
of providing on-line documentation
There's a neat
page, which is subtitled "What Intel Doesn't Want You To Know"
I some hardcopy documentation on DEC Alpha microprocessors. I am willing
to briefly loan them for making selective copies, or I can provide you
with information as to how you can order (for free) your own copy.