Non-Atomic State Transitions
Memory operation involves many actions by many entities, incl. bus
- Look up cache tags, bus arbitration, actions by other controllers, ...
- Even if bus is atomic, overall set of actions is not
- Can have race conditions among components of different operations
Suppose P1 and P2 attempt to write cached block A simultaneously
- Each decides to issue BusUpgr to allow S –> M
Issues
- Must handle requests for other blocks while waiting to acquire bus
- Must handle requests for this block A
- e.g. if P2 wins, P1 must invalidate copy and modify request to BusRdX