This project is offered by Professor Andy Neureuther, neureuth@eecs, 2-4590, 510 Cory. Please see him for further details.
The projects are of interest to Prof. Neureuther for application in the IC and disk head industry and depending on its success there is a possibility it could evolve into a summer job and/or support during the academic year.
The projects are based on extending the PhD work of 1) Alfred Wong on finite-difference time-domain methods in a program TEMPEST developed on CM-2 and CM-5 architectures and ported to a CRAY-YMP and 2) Michael Yeung (finishing PhD in May 1995) on Fast Multipole Methods running on an IBM R/S 6000. Publications on these projects available from professor Neureuther on request. (Thesis of A. Wong, TEMPEST userguide, Paper by Michael Yeung, paper by Bob Socha.)
Porting to the IBM SP2
The IBM SP2 architecture offers both the horsepower for CPU intensive tasks and the convenience of a workstation like environment. It should be straightforward to adapt any of the SAMPLE simulators to a given processor. The challenge will be in exploring ways to utilize multiple processors efficiently. For TEMPEST which is a massively parallel code the communication in sharing results at each time step between processors will be an issue. Improvements may be possible by utilizing the Collective Communications Library (CCL) to group information passing, and by using planes of interface nodes. Also overlapping these planes in buffer interface regions might be advantageous in reducing the frequency of communication calls.
Work on the basic algorithms in TEMPEST is also needed. Several potential improvements in the absorbing boundary conditions have been formulated and are available for testing and tuning to the IBM SP2 architecture in three-dimensions. Fundamental improvements in the discretization for curved material boundaries is also needed.
FAST MULTIPOLE METHODS
The IBM SP2 is attractive for simulation developed on workstations using both nonrigorous (physical optics) and rigorous (boundary integral) approaches based on a code which implements a new extension of the Fast Multipole Method to electrodynamics in 3D. An initial test showed that on the IBM SP2 the code runs 2x slower than on an IBM RISC/6000 model 540 where it takes 2 hours. The code is based on grouping panels which represent the surface in to sets and evaluating their multipole expansions which would nicely parallelize. The rigorous solution is carried out by GMRES methods and their may be existing work on such iterative methods on the IBM SP2 which could be utilized.
FUTURE POSSIBILITY OF WORK ON COMPUTATIONAL GEOMETRY
The SAMPLE group codes involve many computational geometry aspects which might also be of interest on parallel machines. Each surface of a material in the wafer topography is represented by about 5,000 triangles in a data structure with connectivity. These surfaces advance in time and auxiliary Oct Tree sort and is used to efficiently identify when a patch of one surface is about to crash into another surface or cross over itself. A zipper algorithm for finding surface intersections and clipping off or making a swallow tail of the unwanted region is also used. In taking the intersection many small triangles are created and a suite of triangle queries is used to identify thin/small triangles and regularize them without destroying intersections lines, surface ridges etc. The Oct Tree sort takes a few seconds on the RISC/6000 model 540 while the regularizations takes several minutes. Since this advance-intersect-regularize sequence must be performed 30 to 300 times in a single process simulation, their parallelization on the IBM SP2 is of interest.
Background on Rigorous EM Simulation
Topography scattering effects are world class electromagnetic scattering problems which require the very best in modern simulation approaches. Regions as large as 15 wavelengths on a side or over 3,000 wavelengths cubed in volume can contain materials with high and complex refractive indices and must be illuminated with projected images from optical systems with partially coherent illumination. Fortunately several approaches simulating reflective notching problems have been developed at Berkeley under support of the Semiconductor Research Corporation. One of these approaches is to use a finite-difference methods in the time-domain in a program called TEMPEST which has recently been extended to three-dimensions  and shown to be applicable to gate formation . TEMPEST take several minutes of CPU time on a CM-5 machine. With assistance from Los Alamos National Laboratory TEMPEST has been shown to be portable to single instruction machines such as the CRAY-YMP. It would be very interesting to port TEMPEST to the emerging architectures such as that of the IBM-SP2.
A second approach is to utilize a breakthrough in the extension of the formulation of Fast Multipole Methods (FMM) to three-dimensional electromagnetic scattering . This new formulation is being incorporated into both a rigorous boundary integral method with iterative solution and a much faster approximate method based on physical optics methods. The FMM takes about 2 hours on a stand alone IBM RISC/6000 model 540 and appears to run 2 times slower on the IBM SP2 architecture on campus.
All three methods are likely applicable to topography scattering effects and which is most effective will likely vary with the detail of the geometry, materials and scattering phenomena.
Background on the Physical Applications
Reflective notching caused by electromagnetic scattering from previously existing device features is a problem common to patterning the magnetic material of the pole tip for disk-heads and in forming MOS gate linewidths as they cross through the bowel shaped region of tightly layed out devices. Technology Computer-Aided-Design (TCAD) tools can be applied to these problems. This involves linking together the use of SAMPLE for aerial images, TEMPEST and Fast Multipole Methods (FMM) for electromagnetic scattering from nonplanar substrate features, and SAMPLE-3D for resist development effects.
These unanticipated contributions of exposure energy are an additional source of unwanted linewidth variation which is highly dependent on small changes in the topography and the alignment of the feature with respect to the topography. In some cases sever changes in linewidth occur and the problem is referred to as one of reflective notching. For example in making disk heads a fine pole tip must be patterned in a permalloy layer as close as possible to an insulated conducting coil which the permalloy layer must also cover. The sloping rise of the permalloy as it ascends the coil creates a nearly geometrical lateral reflection which results in loss of loss of pattern fidelity of the fine pole tip . Similar nearly geometrical lateral scattering effects occur from a blanket polysilicon layer as it rises from the active MOS device area to coat underlying field oxide regions. Here elliptical bowl like structures are formed which can not only scatter but focus unwanted light into nominally unexposed regions . More typically though a thinning of the linewidth is seen near the end of the gate polysilicon as it approaches and crosses up onto the field oxide.
As feature sizes are reduced compared to the height of topography features and the lithography must be performed with less process latitude to achieve nearly the fundamental theoretical limits, topography scattering must be considered as part of the overall design for manufacturability. The contribution of reflective notching to the linewidth variation budget must be understood and traded-off with other more traditional sources of variations such as inter-field tool variations, resist processing variations, etc. While the ultimate measure of these effects is experimental, process simulation offers the potential of systematic assessment and a physical mechanism based framework for characterizing contributions.
 A.K. Wong, and A.R. Neureuther, "Examination of Polarization Effects in Photolithographic Masks Using Three-Dimensional Simulation," Proc. SPIE Vol. 2197, pp. 521-528, 1994.
 R. Socha, A. Wong, M. Cagan, Z. Krivokapic, and A.R. Neureuther, "Effects of Wafer Topography on the Formation of Polysilicon Gates," Proc. SPIE Vol. 2440, to appear, 1995.
 M.S. Yeung and A.R. Neureuther, "Three-Dimensional Reflective-Notching Simulation using Multipole Accelerated Physical-Optics Approximation," Proc. SPIE Vol. 2440, to appear, 1995.
 J.S. Gau, "Photolithography for Integrated Thin-Film Read/Write Heads," Proc. SPIE VOl. 1088, pp. 504-514, 1989.
 M.P. Karnett and M.C. Sarnoff, "Optimizations and Characterizations of Single Layer Resist," Proc. SPIE Vol. 1088, pp. 324-338, 1989.