I am a 4th year EECS PhD student in Prof. Neureuther's lithography research group. My coursework is mostly in the area of CAD, and my research is in the area of TCAD for lithography. My research project is a pattern matching system for locating areas in a mask layout sensitive to non-ideal process effects. I did my undergrad at Carnegie Mellon University. My website can be found at http://inst.eecs.berkeley.edu/~gennari/index.html and my CS267 Homework 0 can be found at http://inst.eecs.berkeley.edu/~gennari/cs267/hw0.html

I am interested in both CAD and lithography, more specifically in combining ideas from both areas into a project that applies CAD algorithms to solving problems in lithography. I'm technically an EE person, but I do a lot of programming. I have written various circuit and lithography simulators/data processors, as well as OpenGL display tools and high-performance geometry engines. I am also interested in creating 3D virtual worlds and robotics. I have never worked on a parallel processor machine, but I think some of the more complex IC layout processing problems would be ideal for implementation on a parallel processor architecture.

I have never written code for a true parallel processor machine but have written multithreaded code to run on dual processor PCs.

I would like to parallelize some of my programs, especially the pattern matcher I'm writing for my research project, but also possibly some parts of 3DWorld and maybe even the Analytic Center Cutting Plane Convex Optimization method of CircuitSolver. I get tired of waiting for the pattern matcher to finish processing a large layout. The largest test case I've run takes about an hour on a 1GHz machine, but I could easily perform larger pattern matching runs if I had the patience to wait for it.

PS Let me know if you have any problems with the websites and if you need any additional info from me. Feel free to make this info available to the other students.