Computer Architecture Questions

(AR)


(Spring 2001 - Wawrzynek & Kubiatowicz):
"Q1: What are precise interrupts?  Why are they useful?  Discuss how to
implement precise interrupts in a modern processor (superscalar,
out-of-order) of your choice.  What is branch prediction?  Why is it
useful?  How does it fit into your example processor?  What other
things do people try to predict?

Q2:
Draw the floorplan for a processor (real or imaginary but realistic).
Include the major functional blocks and their approximate sizes.
Imagine you now have a merged DRAM/logic process.  Assuming an
identical organization and memory hierarchy, how would this affect the
floorplan?  How would the floorplan differ if you could change the
organization or memory hierarchy?

Q3:
What is memory coherency in multiprocessors?  Discuss coherency in a
snoopy bus model.  Describe a series of reads and writes in this
model.  What is consistency?  What is sequential consistency and how
can it be modelled?  Describe the limitation of snoopy-based coherency
models?  What is/are the solutions?  Describe a series of reads and
writes in that model?

Q4:
We want to create a network router from a standard PC.  (For our
purposes, a router will input a packet, examine the packet, make a
decision about where to route the packet based on stored state, and
send the packet out that port.)  Draw a diagram of this system and
trace a packet through this system.  How do we determine the number of
ports that a single PC can support?  What is the bottleneck?  How do
you justify this?  Estimate various execution times, bandwidths, and
latencies."

(Fall 2000 - Wawrzynek & Patterson):
"Q1: Identify the critical paths in microprocessor design. What is the
effect of carry logic on adder delay? Discuss fast adder techniques.

Q2: Discuss issues related to disk drives, trends, today's spec, and
future specs.  Reason about read times for an entire disk and how this
relates to RAIDs and other disk arrays. 

Q3: Discuss the basic issues involved with system implementation
alternatives.   

Q4: Identify some out-of-order (OOO) execution processors. Select one
and describe its operations."

(Spring 2000 - Wawrzynek & Kubiatowicz):
"Q1: Discuss the distinctions between RISC and CISC; compare and contrast
the advantages of one over the other. Discuss whether the RISC/CISC
distinction is still valid today.

Q2: Discuss the detailing of overheads of message communication. How
would you optimize communication?

Q3: Account for the large difference in energy observed between solving
a problem with custom hardware vs. a general purpose processor. List
some of the metrics one might use to decide between a custom ASIC, an
FPGA, or a general purpose processor.

Q4: What is the cache-coherence problem? What are the definitions of sequential
consistency? Discuss the details of snoopy protocols. and about
the typical bus bandwidth. Estimate the maximum number of processors
that would fit on a bus."

(Fall 1999 - Wawrzynek & Kubiatowicz):
"Q1. Describe precise interrupt.  Why is it useful?  Describe exactly how
you would implement it on a 5 stage pipeline.  Draw a rough block diagram of 
an out-of-order execution processor.  Describe how you implement precise
interrupt with respect to that block diagram.  What happens to the
precise interrupt scheme when there is branch mispredictions?

Q2: Given a very simple processor with no cache, no floating point unit,
single issue, everything in order, pipelined processor, estimate the
number of transistors it will use.  Given the number of transistors you
just came up with, can you implement it using some state-of-the art FPGA?
What is the rough capacity of the FPGA?  What are some pros and cons of
implementing such a processor on a FPGA if it is possible?  Why would
someone ever want to do such thing in the real world?

Q3: Suppose you want to implement a multiprocessor over the conventional
network (like ethernet), describe all the mechanisms you need to pass a message
from one user to another user.  Estimate the time it takes for the
message to go through each part of the process.  Given the time you just
estimated, is it fast enough to meet the need of implementing
multiprocessor?  How can you improve the speed?  How can you protect
users from interfering each other if they have control over the network
hardware?

Q4: Define energy efficiency.  Given that you have a 4-way super-scalar
processor, a program, and the data input, describe how (including
hardware
setup) you can measure the energy efficiency of this processor.  What
would be the issue if you want to compare this energy efficiency number
with other processors?  If you are a chief architect, what kind of
processor you would design to optimize energy efficiency?"

(Spring 1999 - Patterson & Kubiatowicz):
"Q1: What are the causes of cache misses (three C's)? Describe how to
remove these. Under what circumstances would they be advantageous? 

Q2: What is the definition of precise interrupts and the implementation
of precise interrupts in a five-stage pipeline? Discuss modern
superscalar processors.

Q3: Discuss some of the issues behind the replacement of buses with
routers. What are some advantages of router-like architectures?

Q4: Discuss computational paint."

(Fall 1998 - Patterson & Kubiatowicz):
"Q1: What is the definition of precise interrupts and the implementation
of precise interrupts in a five-stage pipeline? Discuss modern
superscalar processors.

Q2: What are the consequences of increased wire delay? How would you
evaluate ambiguous design alternatives?

Q3: Discuss the basic message communication path. Why would a separate
network be needed to avoid protocal overhead? 

Q4: (A database design problem was given.) Calculate the numbers of
disks and CPUs for 100% utilization as well as bus organization. What
does the queueing theory suggest?"


August 2000