Discussion 9

10/22/02 Tue


Disk

A computer has a hierarch of storage from register to tapes. In the memory hiearchy, disk provides the non-volatile storage and reasonable cost/MB and access time.

 

Access Time

Cost/MB

Volatile?

Where is data stored?

Register

Fastest

Highest

Volatile

Flip-flop

Cache

 

 

Volatile

SRAM

Memory

 

 

Volatile

DRAM

Disks

 

 

Non-volatile

Ferromagnetic platter

Tapes

Slowest

Lowest

Non-volatile

Ferromagnetic tape

A disk consists of ferroelectric platters, a moving arm and the headers. The headers read and write bits by using the induced magnetic field and current.

The disk access time can be calculated as follows:

Disk latency = average seek time + average rotational delay + transfer time + controller overhead.

Where seek time is the time to move heads to the right cylinder. Rotational delay is the time to wait before the header reads a sector.

In terms of performance, we are interested in capacity, transfer rate, rotation/seek time and MB/$. Capacity and MB/$ increases pretty fast (2x/1.0year), but rotation and seek time increases pretty slow (1/2 in 10 years).

Network

How is a message transmitted over the network?

1.      Application copies data to OS buffer. (sender overhead)

2.      OS calculates checksum and sens data to the network interface HW. (sender overhead)

3.      Data is transmitted through underlying hardware. (transfer time)

4.      OS copies data from network interface HW to OS buffer. And calculates check sum. (receiver overhead)

5.      OS copies data to user address space. (receiver overhead)

There are some performance factors we can think of.

Bandwidth = Transfer Size / transfer time

Transfer time = Round trip time + 1/Bandwidth * TransferSize

Latency = Propagation + Transmit + Overhead (sender and receiver)

What is a logic gate?

A logic gate is a component that computes a function for a given digital input.

For example,

x

y

AND

OR

X

NOT

0

0

0

0

0

1

0

1

0

1

1

0

1

0

0

1

 

1

1

1

1

Given two binary inputs x and y, x AND y outputs 1 only when x and y are 1. And x OR y outputs either x or y is 1. Given a binary input x, NOT x is returns 1 when x is 0, 0 when x is 1.
Any kind of logic can be represented as a combination of AND, OR and NOT.

Example

X

Y

Out

0

0

1

0

1

0

1

0

0

1

1

1

When does the output have 1?

X = 0, Y = 0 or X = 1, Y = 1

We can write the answer as follows:

XY + XY

Any logic can be represented as a sum of products, and this is a two level logic.

PLA (Programmable Logic Array)

We know that two make a logic is to find a number of products (which is ANDed) and sum those products (by OR). PLA provides a number of connection from inputs and outputs, then the user can simply choose contacts for the corresponding logic. And this is faster than connecting AND, OR, NOT logic gates individually.

Example,

We want to make a logic XY + XY using PLA. Make contacts in the following layout.

Hardware Description Language

Hardware Description Language (HDL) describes logic circuits using programming language.

Verilog and VHDL are widely used HDLs. In CS61C, we learn Verilog.

Example

module xnor(X, Y, Z);

input X, Y;

output Z;

wire notX, notY, XY, notXnotY;

not

(notX, X);

(notY, Y);

and

(notXnotY, notX, notY);

(XY, X, Y);

or

(Z, XY, notXnotY);

End;

 

Sequential Logic

Up to now we discussed combinational logic which only depends on the inputs.

In sequential logic, they use feedback to store a state. In sequential logic, the current logic value depends on not only the inputs but also the previous logic value.

RS-latch

S R Q

0 0 hold (keep value)

0 1 0

1 0 1

1 1 unstable

 

 

Problem of RS latch.

It goes to unstable state when SR = 11.

Input signal R and S should change simultaneously. Otherwise, it can go to an unstable state for a short time.

Flip-flop

Control when input can affect the states using clock signal.

 

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Revised: 10/20/02.