Publications | John Wawrzynek

Pending Publication

Lazzaro, J., Wawrzynek, J., "A Tilt Filter in a Servo Loop", Proceedings of the 133rd Audio Engineering Society (AES), Oct. 26-29, 2012, San Francisco, CA. [PDF]

Ilia Lebedev, Christopher Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, and John Wawrzynek, "Exploring Many-Core Design Templates for FPGAs and ASICs," International Journal of Reconfigurable Computing, Volume 2012 (2012), Article ID 439141, 15 pages, doi:10.1155/2012/439141. [PDF]

Mingjie Lin, Yu Bai, John Wawrzynek, "Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience," Journal of Electrical and Computer Engineering, Volume 2012 (2012), Article ID 593532, 12 pages, doi:10.1155/2012/593532. [PDF]

Lin, M., and Wawrzynek J., "Improving FPGA Placement with Dynamically Adaptive Stochastic Tunneling," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, (December 2010), pp. 1858-1869. DOI=10.1109/TCAD.2010.2061670. [PDF]

Lin, M., Wawrzynek, J., El Gamal, A., "Exploring FPGA Routing Architecture Stochastically," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, no.10, pp. 1509-1522, Oct. 2010, doi: 10.1109/TCAD.2010.2061530. [PDF]

K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. Kubiatowicz, N. Morgan, D. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. Yelick. "A View of the Parallel Computing Landscape" Communications of the ACM, vol. 52 no. 10, pp. 56-67, Oct 2009. [PDF]

J. Rabaey, D. Burke, K. Lutz, and J. Wawrzynek, "Workloads of the Future," IEEE Design and Test of Computers, vol. 25, no. 4, July/August 2008, pp. 358-365. [PDF]

J. Wawrzynek, D. Patterson, M. Oskin, S. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanovic. "RAMP: A Research Accelerator for Multiple Processors," IEEE Micro, vol. 27, no. 2, Mar/Apr 2007, pp. 46-57. [PDF]

A. DeHon, R. Huang, and J. Wawrzynek. "Stochastic Spatial Routing for Reconfigurable Networks," Journal of Microprocessors and Microsystems, Volume 30, Issue 6, 4 Sep 2006, pp. 301-318. [PDF]

A. DeHon, Y. Markovsky, E. Caspi, M. Chu, R. Huang, S. Perissakis, L. Pozzi, J. Yeh, J. Wawrzynek. "Stream Computations Organized for Reconfigurable Execution," Journal of Microprocessors and Microsystems, Volume 30, Issue 6, 4 sep 2006, pp. 334-354. [PDF]

C. Chang, J. Wawrzynek, and R. W. Brodersen. "BEE2: A High-End Reconfigurable Computing System," IEEE Design and Test of Computers, 22(2):114--125, Mar/Apr 2005. [PDF]

T. Callahan, J. Hauser, and J. Wawrzynek. "The Garp Architecture and C Compiler," IEEE Computer, April 2000.

J. Lazzaro, J. Wawrzynek, and R. P. Lippmann. A Micropower Analog Circuit Implementation of Hidden Markov Model State Decoding. IEEE Journal Solid State Circuits 32:8, 1200-1209, August 1997.

J. Lazzaro and J. Wawrzynek, "JPEG Quality Transcoding Using Neural Networks Trained with a Perceptual Error Measure," Neural Computation, Vol. 11, No. 1, January 1999.

J. Lazzaro and J. Wawrzynek. "Speech Recognition Experiments with Silicon Auditory Models," Analog Integrated Circuits and Signal Processing An International Journal, 13:1-2. 37-51, 1997.

J. Wawrzynek, K. Asanovic, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan. SPERT-II: A Vector Microprocessor System. IEEE Computer, March 1996.

J. Lazzaro, J. Wawrzynek, and A. Kramer. Systems Technologies for Silicon Auditory Models. IEEE Micro, 14(3):7-15, June 1994.

K. Asanovic, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek. "Designing a Connectionist Network Supercomputer", International Journal of Neural Systems, 4(4):317-326, December 1993.

J. Wawrzynek, K. Asanovic, and N. Morgan. "The Design of a Neuro-Microprocessor", IEEE Journal on Neural Networks, 4(3), 1993.

J. Lazzaro, J. Wawrzynek, M. Mahowald, M. Sivilotti, and D. Gillespie. "Silicon Auditory Processors as Computer Peripherals," IEEE Journal on Neural Networks, 4(3):523-528, 1993.

K. Asanovic, N. Morgan, and J. Wawrzynek. "Using Simulations of Reduced Precision Arithmetic to Design a Neuro-Microprocessor", Journal of VLSI Signal Processing, 6:33-44, June 1993.

Bachrach, J., Vo, H., Richards, B., Lee, Y., Waterman, A., Avizienis, R., Wawrzynek, J., and Asanovic, K., "Chisel: Constructing Hardware in a Scala Embedded Language," Proceedings of 2012 Design Automation Conference (DAC), June 3-7, 2012, San Francisco, pp. 1216-1225, http://doi.acm.org/10.1145/2228360.2228584. [PDF]

Cheng S., Lin, M., Liu, H., Scott, S., Wawrzynek, J., "Exploiting Memory-Level Parallelism in Reconfigurable Accelerators," 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines (FCCM 2012), April 29 - May 1, 2012, Toronto, Canada, pp. 157-160. [PDF]

Mingjie Lin, Yu Bai, John Wawrzynek, "Discriminatively Fortified Computing with Reconfigurable Digital Fabric," 13th IEEE International Symposium on High-Assurance Systems Engineering (HASE 2011), Boca Raton, FL, USA, Nov. 10-12, 2011. IEEE Computer Society 2011, ISBN 978-1-4673-0107-7, pp. 112-119. [PDF]

Christopher W. Fletcher, Ilia A. Lebedev, Narges Bani Asadi, Daniel Burke, John Wawrzynek, "Bridging the GPGPU-FPGA Efficiency Gap," Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2011), Monterey, CA, Feb 27 - Mar 1, 2011, pp. 119-122. [PDF]

I. Lebedev, S. Cheng, A. Doupnik, J. Martin, C. Fletcher, D. Burke, M. Lin, and J. Wawrzynek, "MARC: A Many-Core Approach to Reconfigurable Computing," Proceedings of 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), Dec 13-15, 2010, Cancun, Mexico, pp. 7-12. [PDF]

Mingjie Lin and John Wawrzynek, "Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations," Proceedings of 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010), Dec 13-15, 2010, Cancun, Mexico, pp. 103-108. [PDF]

John Wawrzynek, Mingjie Lin, Ilia Lebedev, Shaoyi Cheng, and Daniel Burke, "Rethinking FPGA Computing with a Many-Core Approach," The First Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010), Atlanta, Georgia, Dec 5, 2010, [PDF]

Mingjie Lin, Ilia Lebedev, and John Wawrzynek, "OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices," Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL2010), Aug. 31st - Sep. 2nd, 2010, pp 458-463. [PDF]

N. B. Asadi, C. W. Fletcher, G. Gibeling, E. N. Glass, K. Sachs, D. Burke, Z. Zhou, J. Wawrzynek, W. H. Wong, G. P. Nolan, "ParaLearn: A Massively Parallel, Scalable System for Learning Interaction Networks on FPGAs," Proceedings of the 24th ACM International Conference on Supercomputing, Tsukuba, Ibaraki, Japan, Jun 02-04, 2010. Pages: 83-94. Best Student Paper Award [PDF]

M. Lin, I. Lebedev, and J. Wawrzynek, "High-Throughput Bayesian Computing Machine with Reconfigurable Hardware," Proceedings of the Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 21-23, 2010, pp. 73-82. [PDF]

Yury Markovsky, Yatish Patel, and John Wawrzynek, "Using adaptive routing to compensate for performance heterogeneity," 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS 2009), May 10-13, 2009, San Diego, CA, pp. 12-21. [PDF]

M. Mohiyuddin, M. Murphy, L. Oliker, J. Shalf, John Wawrzynek, and Samuel Williams, "A Design Methodology for Domain-Optimized Power-Efficient Supercomputing," Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC '09), Article No.: 12 doi>10.1145/1654059.1654072, November 2009. [PDF]

D. Burke, J. Wawrzynek, K. Asanovic, A. Krasnov, A. Schultz, G. Gibeling, P.-Y. Droz. "RAMP Blue: Implementation of a Multicore 1008 Processor FPGA System" Proceedings of the Reconfigurable Systems Summer Institute 2008, National Center for Supercomputing Applications, University of Illinois at Urbana-Champaign, July 7-8, 2008. [PDF]

Y. Markovsky and J. Wawrzynek. "On the Opportunity to Improve System Yield With Multi-core Architectures," in IEEE International Workshop on Design for Manufacturability and Yield, Santa Clara, CA, October 25-26, 2007. [PDF]

A. Krasnov, A. Schultz, J. Wawrzynek, G. Gibeling, and P. Droz. "RAMP Blue: A Message-Passing Many Core System in FPGAs," Proceedings of FPL 2007, 17th International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands, 27-29 August 2007, pp. 54-61. [PDF]

A. Parsons, D. Backer, C. Chang, D. Chapman, H. Chen, P. Crescini, C. de Jesus, C. Dick, P. Droz, D. MacMahon, K. Meder, J. Mock, V. Nagpal, B. Nikolic, A. Parsa, B. Richards, A. Siemion, J. Wawrzynek, D. Werthimer, and M. Wright, "PetaOp/Second FPGA Signal Processing for SETI and Radio Astronomy," Proceedings of the Asilomar Conference on Signals, Systems, and Computers, Oct 29 - Nov 1, 2006, pp. 2031-2035. [PDF]

D. Patterson, Arvind, K. Asanovic, D. Chiou, J. C. Hoe, C. Kozyrakis, Shih-Lien Lu, M. Oskin, J. Rabaey, and J. Wawrzynek. "RAMP: Research Accelerator for Multiple Processors," HotChips 18, A Symposium on High Performance Chips, Aug 20-22, 2006. [PDF]

C.R. Baker, Y. Markovsky, J. van Greunen, J. Rabaey, J. Wawrzynek, A. Wolisz, "ZUMA: A Platform for Smart-Home Environments", Proceedings of the 2nd International Conference on Intelligent Environments IE06, National Technical University of Athens, Greece, 05-06 July 2006, pp. 51-60. [PDF]

J. van Greunen, Y. Markovsky, C. R. Baker, J. Rabaey, J. Wawrzynek, A. Wolisz "ZUMA: A Platform for Smart Home Environments, The Case for Infrastructure", Proceedings of the 2nd International Conference on Intelligent Environments IE06, National Technical University of Athens, Greece 05-06 July 2006, pp. 257-266. [PDF]

Z. Hyder and J. Wawrzynek. "Defect Tolerance in Multiple-FPGA Systems," IEE Proceedings on Computers and Digital Techniques, May 2006, Volume 153, Issue 3, pp. 139-145. [PDF]

Chen Chang, John Wawrzynek, Robert W. Brodersen. "Design & Application of BEE2 - a High-end Reconfigurable Computing System," HotChips 17, A Symposium on High Performance Chips, Aug 14-16, 2005. [PDF]

C. Chang, J. Wawrzynek, P. Droz, R. W. Brodersen, "The Design and Application of a High-End Reconfigurable Computer System," Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2005), pp. 129-136, June 2005. [PDF]

Z. Hyder and J. Wawrzynek. "Defect Tolerance in Multiple-FPGA Systems," Proceedings of IEEE 15th International Conference on Field Programmable Logic and Applications (FPL2005), Aug 24--26, 2005. Best Paper Award [PDF]

Lazzaro, J. P., Wawrzynek, J. "An RTP Payload Format for MIDI." The 117th Convention of the Audio Engineering Society (AES), October 28-31, 2004, San Francisco, CA, USA. [PDF]

Nicholas Weaver, John Hauser, and John Wawrzynek, "The SFRA: A Corner-Turn FPGA Architecture", the 12th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2004. [PDF]

J. Yeh and J. Wawrzynek. "Compute-Resource Allocation for Motion Estimation in Real-Time Video Compression," Asilomar Conference on Signals, Systems, and Computers, November 2003. [PDF]

Joseph Yeh and John Wawrzynek. "Quality Based Compute-Resource Allocation in Real-time Signal Processing," Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 03), Apr 6-10, 2003.

Nicholas Weaver, Yury Markovskiy, Yatish Patel, and John Wawrzynek. "Post Placement C-slow Retiming for the Xilinx Virtex FPGA," Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA 2003) February 23--25, 2003.

Randy Huang, John Wawrzynek, and Andre DeHon. "Stochastic, Spatial Routing for Hypergraphs, Trees, and Meshes," Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA 2003) February 23-25, 2003.

Y. Markovskiy, E. Caspi, R. Huang, J. Yeh, M. Chu, J. Wawrzynek, and A. DeHon. "Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine," Proceedings of the Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002) Feb. 24-26, 2002.

A. DeHon, R. Huang, and J. Wawrzynek. "Hardware-Assisted Fast Routing," Proceedings of the IEEE Symposium on Field-Programmable Gate Arrays for Custom Computing Machines (FCCM2002) , April 22-24, 2002.

E. Caspi, R. Huang, Y. Markovskiy, J. Yeh, J. Wawrzynek, and A. DeHon. "A Streaming Multi-Threaded Model," Third Workshop on Media and Stream Processors (MSP-3) , December 2, 2001.

J. P. Lazzaro and J. Wawrzynek. "A Case for Network Musical Performance." The 11th International Workshop on Network and Operating Systems Support for Digital Audio and Video (NOSSDAV 2001), June 25-27, 2001, Port Jefferson, New York.

J. P. Lazzaro and J. Wawrzynek. "Compiling MPEG 4 Structured Audio into C." Proceedings of the Second IEEE MPEG-4 Workshop and Exhibition (WEMP) June 18-20, 2001, San Jose, CA.

T. Callahan and J. Wawrzynek. "Adapting Software Pipelining for Reconfigurable Computing," Published in Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES2000) , November 17-18, 2000.

E. Caspi, M. Chu, R. Huang, J. Yeh, J. Wawrzynek, and A. DeHon "Stream Computations Organized for Reconfigurable Execution (SCORE)," Proccedings of Conference on Field Programmable Logic and Applications (FPL 2000), August 28--30, 2000).

N. Weaver and J. Wawrzynek. "A Comparison of the AES Candidates Ameanability to FPGA Implementation," Proceeding of the Third Advanced Encryption Standard Candidate Conference, (April 13-14, 2000)

A. DeHon and J. Wawrzynek. "Reconfigurable Computing: What, Why, and Design Automation Requirements?" Proceedings of the 1999 Design Automation Conference (DAC 1999, June 21-25, 1999)

S. Perissakis, Yangsung Joo, Jinhong Ahn, A. DeHon, and J. Wawrzynek. "Embedded DRAM for a Reconfigurable Array." Proceedings of the 1999 Symposium on VLSI Circuits (VLSI 1999, June 17-19, 1999).

T. Hodes, J. Hauser, A. Freed, J. Wawrzynek, and D. Wessel, "A Fixed-Point Recursive Digital Oscillator for Additive Synthesis of Audio," Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, Phoenix, AZ, March 1999.

W. Tsu, K. Macy, A. Joshi, R. Huang, J. Wawrzynek, et al., "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," AGM/SIGDA Int. Symp. Field Programmable Gate Arrays, Monterey, CA, February 1999.

T. J. Callahan and J. Wawrzynek, "Instruction-level Parallelism for Reconfigurable Computing," Proc. Int. Workshop Field-Programmable Logic and Applications, from FPGAs to Computing Paradigm, Tallinn, Estonia, August-September 1998.

T. Callahan, P. Chong, A. DeHon, and J. Wawrzynek. "Fast Module Mapping and Placement for Datapaths in FPGAs." Published in Proc. of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays (FPGA 1998), February 22-24, 1998.

M. Chu, N. Weaver, K. Sulimma, A. DeHon, and J. Wawrzynek. "Object Oriented Circuit-Generators in Java." Published in Proc. of the International Symposium on Field-Programmable Gate Arrays for Custom Computing Machines (FCCM 1998), April 15-17, 1998.

J. R. Hauser and J. Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor, In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 97, April 16-18, 1997), pp. 24-33.

J. Lazzaro, J. Wawrzynek, and R. Lippmann. A Micropower Analog VLSI HMM State Decoder for Wordspotting, in Advances in Neural Information Processing Systems 9 (NIPS96), Proceedings of the 1996 Conference, M. C. Mozer, M. Jordan, and T. Petsche, Eds., Cambridge, Mass: MIT Press, (1996).

K. Asanovic, J. Beck, B. Irissou, B. Kingsbury, and J. Wawrzynek. T0: A Single-Chip Vector Microprocessor with Reconfigurable Pipelines. Proceedings of the 22nd European Solid-State Circuits Conference, September 1996, pp. 344-347.

T. Callahan and J. Wawrzynek. "A Simple Profiling System for SUIF", The First SUIF Compiler Workshop, Stanford University, January 1996.

Krste Asanovic, James Beck, Bertrand Irissou, Brian E. D. Kingsbury, Nelson Morgan, and John Wawrzynek. "The T0 Vector Microprocessor", In Proceedings of Hot Chips VII, August 1995.

J. Lazzaro and J. Wawrzynek. "Silicon Models for Auditory Scene Analysis", In Michael Hasselmo, David Touretzky, and Michael Mozer, editors, Advances in Neural Information Processing Systems5 (NIPS95), Proceedings of the 1995 Conference. MIT Press, December 1995.

J. Wawrzynek, K. Asanovic, B. Kingsbury, J. Beck, D. Johnson, and N. Morgan. "SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training", In Michael Hasselmo, David Touretzky, and Michael Mozer, editors, Advances in Neural Information Processing Systems5 (NIPS95), Proceedings of the 1995 Conference. MIT Press, December 1995.

J. Lazzaro and J. Wawrzynek. "A Multi-Sender Asynchrounous Extension to the AER Protocol", In 1995 Conference on Advanced Research in VLSI. IEEE Computer Society, 1995.

K. Asanovic, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek. "A Supercomputer for Neural Computation", In Proceedings of the International Conference on Neural Networks, volume 1, pages 5-9, 1994.

K. Asanovic, J. Beck, J. Feldman, N. Morgan, and J. Wawrzynek. "Development of a Connectionist Network Supercomputer", In Proceedings of the Third International Conference on Microelectronics for Neural Networks, pages 253-262, Edinburgh, Scotland UK, April 1993. UnivEd Technologies Ltd, University of Edinburgh.

J. Wawrzynek and B. Irissou. "High Speed 64-bit CMOS Datapath", In G. Borriello and C. Ebeling, editors, Research on Integrated Systems, Proceedings of the 1993 Symposium, pages 143-154, Seattle, Washington, March 1993. The MIT Press.

J. Lazzaro, J. Wawrzynek, M. Mahowald, M. Sivilotti, and D. Gillespie. "Silicon Auditory Processors as Computer Peripherals", In Stephen José Hanson, Jack D. Cowan, and C. Lee Giles, editors, Advances in Neural Information Processing Systems 5, Proceedings of the 1993 Conference, pages 820-827. Morgan Kaufmann Publishers, December 1992.

K. Asanovic, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek. SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations. In José Fortes, Edward Lee, and Teresa Ming, editors, Proceedings of the International Conference on Application Specific Array Processors, pages 178-190. IEEE Computer Society Press, August 1992.

K. Asanovic, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek. SPERT: A VLIW/SIMD Neuro-Microprocessor. In Proceedings of the International Joint Conference on Neural Networks, pages 577-582, 1992.

P. de Dood, J. Wawrzynek, E. Liu, and R. Suaya. A Two-Dimensional Topological Compactor Using Octagonal Geometry. In Proceedings of the 28th ACM/IEEE Design Automation Conference. ACM Press, June 1991.

A. Cassotto, B. Kingbury, and J. Wawrzynek. Using VOV, an Automated Design Manager, in a VLSI Design Course. In Gaetano Borriello, editor, Microelectronic System Education Conference, pages 51-59, July 1991.

D. Culler, A. Sah, K. Schauser, T. von Eicken, and J. Wawrzynek. Fine-grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. In Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, April 1991.

E. Liu, P. de Dood, R. Suaya, and J. Wawrzynek. A Topological Framework for Compaction and Routing. In Carlo H. Séquin, editor, Proceedings of the 13th Conference on Advanced Research in VLSI, pages 212-228. The MIT press, 1991.

K. Asanovic, B. Kingsbury, N. Morgan, and J. Wawrzynek. A Highly Piplined Architecture for Neural Network Training. In IFIP Workshop on Silicon Architectures for Artificial Neural Networks, November 1990.

J. Wawrzynek and T. von Eicken. VLSI Parallel Processing for Musical Sound Synthesis. In Proceedings of the International Computer Music Conference, Glasgow, Scotland, September 1990.

S. Pointer and J. Wawrzynek. Multimedia Digital Signal Processing Tutoring System. In Proceedings of the International Computer Music Conference, Glasgow, Scotland, September 1990.

D. Wessel, R. Felciano, A. Freed, and J. Wawrzynek. The Center for New Music and Audio Technologies. In Proceedings of the International Computer Music Conference, Ohio State University, November 1989. Invited paper.

J. Wawrzynek and T. von Eicken. MIMIC, A Custom VLSI Parallel Processor for Musical Sound Synthesis. In G. Musgrave and U. Lauther, editors, Proceedings of the IFIP IC10/WG10.5 Working Conference on Very Large Scale Integration, Munich, FRG, August 1989.

B. Richards, C. Chang, J. Wawrzynek, and R. Brodersen, "Programming Streaming FPGA Applications Using Block Diagrams in Simulink," in S. Hauck and A. DeHon (ed), Reconfigurable Computing, Morgan Kaufmann Publishers, Burlington, MA, 2008, Chapter 8, pp. 183-202. [protected PDF]

J. P. Lazzaro and J. Wawrzynek. "Substractive Synthesis without Filters," in Audio Anecdotes II, edited by Ken Greenebaum and Ronen Barzel, A.K. Peters, publisher, 2004. [PDF]

Lazzaro, J. P., Wawrzynek, J., "Speech recognition experiments with silicon auditory models," In Lande, T. S. (ed), Neuromorphic systems engineering : neural networks in silicon. Boston : Kluwer Academic, 1998.

K. Asanovic, J. Beck, B. Kingsbury, N. Morgan, and J. Wawrzynek. Training Neural Networks with SPERT-II, In Parallel Architectures for Artificial Neural Networks, Paradigms and Implementations. N. Sundrarajan and P. Saratchandran, editors, 1998, IEEE Computer Society, pp. 345-364.

J. Lazzaro and J. Wawrzynek. Low-Power Silicon Neuron, Axons, and Synapses. In M. E. Zaghloul, J. Meador, and R. W. Newcomb, editors, Silicon Implementation of Pulse Coded Neural Networks. Kluwer Academic Publishers, 1993.

J. Wawrzynek. VLSI Models for Real-time Music Synthesis. In M. Mathews and J. Pierce, editors, Current Directions in Computer Music Research. MIT Press, 1989.

Internet IETF RFC Series

Lazzaro, J. P., Wawrzynek, J. (2011). RTP Payload Format for MIDI. RFC 6295, Internet Engineering Task Force (IETF) Proposed Standard Protocol. http://www.rfc-editor.org/rfc/rfc6295.txt

Lazzaro, J. P., Wawrzynek, J. (November 2006). "An Implementation Guide for MIDI". RFC 4696, Internet Engineering Task Force (IETF) Standards Track (Informational). Protocol. http://tools.ietf.org/html/rfc4695.txt.

Technical Reports

Asanovic, K., R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. D. Kubiatowicz, E. A. Lee, N. Morgan, G. Necula, D. A. Patterson, K. Sen, J. Wawrzynek, D. Wessel, and K. A. Yelick, "The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View", Technical Report No. UCB/EECS-2008-23, Mar 2008. [PDF]

Arvind (MIT), Krste Asanovic (MIT), Derek Chiou (UT Austin), James C. Hoe (CMU), Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Mark Oskin (U Washington), David Patterson (UC Berkeley), Jan Rabaey (UC Berkeley), and John Wawrzynek (UC Berkeley), "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform," Technical Report UCB//CSD-05-1412, September 2005.

K. Asanovic, J. Beck, T. Callahan, J. Feldman, B. Irissou, B. Kingsbury, P. Kohn, J. Lazzaro, N. Morgan, D. Stoutamire, and J. Wawrzynek. CNS-1 Architecture Specification. Technical Report TR-93-021, International Computer Science Institute, April 1993.

B. Kingsbury, K. Asanovic, B. Irissou, N. Morgan, and J. Wawrzynek. Recent work in VLSI elements for digital implementations of Artificial Neural Networks. Technical Report TR-91-074, International Computer Science Institute, 1991.

K. Asanovic, J. Beck, B. Kingsbury, P. Kohn, N. Morgan, and J. Wawrzynek. SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations. Technical Report TR-91-072, International Computer Science Institute, 1991.

N. Morgan, K. Asanovic, B. Kingsbury, and J. Wawrzynek. Developments in Digital VLSI design for Artificial Neural Networks. Technical Report TR-90-065, International Computer Science Institute, 1990.