| 1: | BIGMOUTH | ||
| Project Partners: Joe Suh and James Chien and Thomas Lee and Danh Nguyen | |||
| Section: 101 | |||
| We will be focusing on a number of "mini-projects" to enhance our datapath. We plan to add a victim cache, branch prediction and multiplier/divider. To top it all off, we'll add a slice of not so deep pipelining.
Talks about other processors behind their backs. For example, on 12/9/99, Bigmouth was quoted as saying "A group of 3 and STILL we manage to get 3rd place (a close 2nd) in the competition. Who's your daddy!?" | |||
| 2: | Moctezuma | ||
| Project Partners: Woojin Yu and Chuong Pham and Wilson Cheung and Erik Olson and Woongeun Jung | |||
| Section: 101 | |||
| We will be serving a processor with Tomasulo architecture, reorder buffer, and a scent of branch prediction. We will implement the processor with equal proportions of hardware and VHDL. | |||
| 3: | Haste Makes Waste | ||
| Project Partners: David Chang and Tony Tseng and Mark Chuang and Gregory Lawrence and Chris Shumway | |||
| Section: 101 | |||
| Our final project will be a multiprocessor with TLB, second level cache, and a multiplier/divider. | |||
| 4: | A team of five, and two processors (A.K.A. a Gift for Grandma - GFG) | ||
| Project Partners: Celia La and Tun-I Kok and Sut-Hong Chan and Shengliang Song and John Pham | |||
| Section: 101 | |||
| We are doing a multiprocessor with second level caches, stream buffers, and store buffers. | |||
| 5: | La Valium | ||
| Project Partners: Nikhil Acharya and Yi-Chun Eugenia Chien and John Loo and Yuet Shun Suen and Sam Wu | |||
| Section: 102 | |||
| We will be implementing a 5-stage 2-way superscalar pipeline. Branches will be taken in the EX stage, and to reduce the average penalty for taking branches in the EX stage, we will employ a 2-level predictor. In order to deal with memory latency, the processor will incorporate prefetching in the form of a 4 word stream buffer.
Initial design drafted and perfected on restaurant napkin. | |||
| 6: | BACH's Suzy Q Super Proc (BSQSP) | ||
| Project Partners: Brian Oh and Alan Chou and Chris Spitzer and Henry Kang | |||
| Section: 102 | |||
| An overture to our beloved Suzy Q, the BACH team composes a delightful new 2-way super-scalar 5-stage processor, with a nifty victim cache and an instruction stream buffer. We only hope that our design will faithfully reproduce the enthusiasm and dedication we have for our angelic Suzy Q.
folle et sage
Revision: Also plays a CAM-based cache | |||
| 7: | Eclipse | ||
| Project Partners: Vickie Chan and Jason Chen and Jeff Herman and Brenda Liu and Carlo Ordonez | |||
| Section: 102 | |||
| A two-way superscalar pipelined processor with branch and jump target prediction, and (time permitting) load value prediction via register use prediction. | |||
| 8: | A.S.D.F. (Amazingly Super Duper Fast) | ||
| Project Partners: Norman Zhou and Dan Goldberg and Jesse Rankin and Marco Carloni | |||
| Section: 102 | |||
| A two-way superscalar, extended pipeline, and branch prediction for maximum throughput. Also includes a victim cache, write buffer, interleaved bursting DRAMs, and stream buffers to minimize memory latency. | |||
| 9: | Accept Torture, Rich Emu (ATRE) | ||
| Project Partners: Alan Chen and Albert Chen and Chinwuba Ezekwe and James Yeh | |||
| Section: 102 | |||
| We are doing an out of order processor with multiple issue (heavily pipelined).
We are going to have branch prediction, a reorder buffer, and a write buffer.
Essentially, this is going to be a "restaurant quality" processor | |||
| 10: | Definitely outta hand (D'OH!) | ||
| Project Partners: Andrew Yee and Jim Hillman and Richard Allen and Nathan Wooster | |||
| Section: 102 | |||
| A five stage pipleined processor with non-blocking loads, a reorder buffer, and a victim cache. The reorder buffer is used in conjunction with the non-blocking load scheme. | |||