CS152 Computer Architecture and Engineering

Fall 2003, Prof. John Kubitowicz

Lab 2 is due Thursday 2/19.  Be prepared to explain your debugging techniques to your TA during section.  You will also have to checkoff your multiplier during your section on Thursday, 2/19. Your lab report must be submitted by 11:59pm 2/19 (Thursday night) using the submit program (see below).

The Lab is QUITE long, with a STEEP LEARNING CURVE IF YOU HAVE NOT TAKEN EECS 150, so get started early!!!

Homework Policy: Homework assignments are due in class. No late homeworks will be accepted. There will be a short quiz in lecture the day the assignment is due; the quiz will be based on the homework. Study groups are encouraged, but what you turn in must be your own work.

Lab Policy: Labs (including final reports) must be submitted by 11:59pm on the day that the lab is due.. To Submit your lab report, run m:\bin\submit-spring2004.exe or at command prompt, type "submit-spring2004.exe" then follow the instructions. Make sure you input the correct section number,  and directory to submit. Remember that you can only submit once, so make sure to submit only when you're ready. Otherwise your lab/project grade will NOT be correctly recorded. The required format for lab reports is shown on the handouts page.

Homework #2:

Lab #2:

Part 1: Introduction to Xilinx

Part 2: 32 bit Multiplier

As part of this lab, we want you to keep an on-line notebook as discussed in lecture. Be sure to follow these steps:

1. Open the editor of your choice (notepad, word, emacs, etc.) and keep it running while you work. This editor should only be used to maintain your online notebook.

2. When starting a new entry, be sure to record the time and date of that entry. You may type "date" at a unix prompt and copy and paste that in.

3. Write down your goal for that entry.

4. Make notes of any accomplishments, bugs, or insights you may develop as you work. MAKE SURE YOU CAN UNDERSTAND YOUR OWN NOTES!! Students will often write an entry that makes sense to them as they write it, but are incomprehensible a few days later. Write your entry so that you will still be able to understand it in a month. This will be important in later labs as you may want to reference back to old labs.

5. You may want to copy and/or save key waveforms that you get from simulation.

6. At the end of the session, record the time and date. Again, you may type "date" at a unix prompt and copy and paste that in.

Problem 1: Verilog components

In this problem, you will be designing the components that you will need for your multiplier in Verilog. We would like you to implement the 3rd version of the sequential multiplier covered in COD (Pg. 256-257). You will be using Xilinx's Project Navigator to manage your project. The toolflow tutorial you have gone through showed you how to open and create Verilog and schematic files.

1a) Implement the components you will need for your multiplier. Specifically, you will need an adder, a product register, and a multiplicand register.  Each component should be its own Verilog module. You are allowed to use behavioral Verilog for these components.  Be sure to give an overview of how your components are designed in your report. We have included skeleton modules in the M:\lab2 directory. You may add or remove signals to these skeleton modules as you wish. Also, include your Verilog code as appendices in your report.

1b) Test each of your components individually. This is a part of the technique known as incremental testing. By verifying that each of your components works independently, it will make debugging a lot easier later when all the components are put together. We would like you to build test benches for each of your components and run simulation using Modelsim. Include these test benches and relevant Modelsim output in your report. What is your testing methodology?

1c) Assemble your finished components using the Xilinx ECS schematics editor to build your datapath. To do this, you need to create schematic symbols for you Verilog module. First, make sure that the file containing your module is selected in the "Sources in Project" window. Under the "Processes for Current Sources" window, expand the item that says "Design Entry Utilities." Double click on the "Create Schematic Symbol line. Now, you can open up the schematics editor by going to Project -> New Source, and choosing Schematic. Name your datapath multiplier.sch. You will notice that your symbols are ugly rectangle. Learning how to change the appearance of schematic symbols will make your datapath a lot easier to read. To do this, right click on your symbol, highlight the item that says symbol, and then choose edit symbol. Modify your symbols so that your datapath looks like the one in the lecture slides. Note that you cannot connect all of the wire just yet; you still have to do control. Turn in a copy of your datapath after the control is connected (after part 2c).

Problem 2: Control

Now that your datapath is finished, you can give yourself a pat on the back. However, a working datapath is useless without control. Remember the 5 components of a computer?

2a) Read part 2b and 2c before attempting 2a!! Using Verilog, build a controller for your multiplier. As shown and discussed in lecture, your controller should take in the LSB of  the product as input, and produce 3 control signals, one for the adder, one for shifting, and one for the write enable into the product register. Your controller must control your datapath according to the algorithm given in lecture. Look carefully at the skeleton controller we have provided.

2b) Typically in a processor, the values into the multiplicand and multiplier register are placed the register file, but since we don't have a processor (yet!), our controller will have to be able to do this task as well. Therefore, your controller must take in two 32 bit values and a reset signal as well. These will be used to actually give your multiplier something useful to do! The two 32 bit values are the multiplier and the multiplicand. Upon receiving a reset high, your controller will put the multiplier and multiplicand into their respective registers (this means that you may have to add additional outputs from your controller to the datapath that aren't shown in the lecture slide diagrams). Once the reset signal drops back to low, your controller is to begin executing the algorithm.

2c) Write a testbench to test your controller. You may choose to either test parts 2a and 2b separately or all at once after you've finished both parts. Please explain which way you chose, and why.

Problem 3: Tying it all together

3a) Now that we have a functional datapath and control unit, we can finally put them together. The simplest way to do this would be to do this would be to create a schematic for the control unit, and just add the control unit into the datapath you created before. What are the input and output signals (signals to go to or come from the outside world) of your multiplier? What signals are internal to your multiplier? Take your entire multiplier datapath (with the controller), and create a single module. You can do this by creating a seperate module that instantiates your datapath. For example:

module finalMultiplier(value1, value2, answer, clk);
   input [31:0] value1, value2;
   input clk;
   output [63:0] answer;

   datapath myDatapath(....);
endmodule

 Call this file multiplier.v

3b) Simulate your multiplier with a set of judiciously chosen test vectors in a test bench. Explain your criteria for choosing numbers. Turn in a log of your simulation.

3c) Build a top-level Verilog module to take your multiplier through its paces. This top-level module should include your multiplier module, and should apply pseudo-random 32-bit numbers to the multiplier and check that the result is correct, and print out the results in the following form:

    1: number1 * number2 = result
    2: number3 * number4 = result
    3: number5 * number6 = result
    4: number7 * number8 = result
                        .
                        .
                        .

    If there is ever a failure, you should flag it, like this:

        >>>ERROR<<<
        >>>5: number9 * number10 = result
        >>>        Should be: realresult
 

If you tested well in the previous two parts, you should probably find little, if any, error messages. You should be able to run this random vector test for a long time, but try a small number of results first. Turn in a trace from a 100-number loop. Turn in a list of your code and a trace of your output.

Hint:  here you will want to use Verilog system functions. There is the $random function to get random values and the $display function to print results. There is an online Verilog manual under the handouts sections. Look at chapter 17 (17.1 talks about $display and 17.9 talks about $random).

Problem 4: Going to board!

Now we get to the exciting part!
NOTE: If you're having problems with your multiplier working on the board (but not in simulation) you may wish to skip to Problem 5 to do some hardware debugging.

4a) In this part, you will be pushing your multiplier down to the Calinx board. This involves using the Synplify tool to create a netlist, the Xilinx tools to place and route the design, and finally the Xilinx iMPACT tool to send the created bitstream to the board. Please note that this is a very complicated process, especially for people who have never done it before. Follow the steps in the tutorial and during the demo, and ask your TAs or fellow students who have taken EECS150 recently for help.

4b) We have provided you with a top-level wrapper module, called top_level.v. The top_level module will connect your multiplier to the input/output pins of the FPGA, which will allow you to take in actual inputs from the board, and display your results on the hex LEDs.We will be using the dipswitches on the board as input to the multiplier, one of the push buttons to be the reset button, and the hex LED as output. Look inside the top_level.v, there are a lot of comments inside that tell you what to do.

4c) Look at your Xilinx reports. How many LUTs did your multiplier use? How many Slices?

4c) You will need to demo your completed multiplier on the board to your TA during your section, so save all of your files.

Problem 5: ChipScope

Now it's time for some super fun hardware debugging.

You should add ChipScope ICON and ILA modules to your design (either through the core generator or the core inserter) and use them to do some debugging. Even if your design works properly you should not skip this step because it will teach how to use the hardware debugging tools on later labs where your project will almost never work on the first try.

Setup a trigger to run during the execution of the multiply that will give a snapshot of the product register and some of the important control wires during the 16th cycle of the multiplication process. Show this nifty functionality to your TA during the checkoff.

Extra Credit:

This section is intended for students who have taken EECS150 and who may otherwise find this lab too easy.

Problem 1: Fast Multiplier

In addition to the 32 cycle mulitplier that you built, build a faster multiplier.  Some examples of faster multiplication schemes include Booth's Algorithm (found on Pg. 259 of COD), an array multiplier, and a Wallace Tree multiplier.  It is NOT acceptable to use a * in verilog to make your multiplier.  Often one option on the final project is a faster multiplier so doing this now could save you some work later.  Finally, at the end of the semester any working final projects will be placed in head-to-head races to the death so a fast multiplier could be a very useful...

Problem 2: Extended Control

Modify your controller to calculate the factorial of the input from one of the dipswitches.  Upon pushing another button besides the reset button you selected in 4b, the number on one of the dipswitches should serve as an input to your factorial circuit.  Just as before the results should be displayed on the hex LEDs.  By default the lower 32 bits of the results should be displayed, and by pushing another button or toggling a dipswitch the upper 32 bits of the result should be displayed.  Do not worry about factorial results that will exceed 64 bits.