CS252: Homework Assignment #1 Due Friday, October 13th

4.2, 4.5[Also, show any startup and/or cleanup code - i.e. the resulting loop should be self-contained]

4.7, 4.8, 4.10, 4.11

4.14 [parts (c) and (d) only: blank figures available: postscript scoreboard, xfig .fig scoreboard, postscript Tomasulo status, and xfig .fig Tomasulo status are available if you would like to use them. (The .figs are included in case you need to modify or improve the figure]

4.19 [except: assume latency of ADDD was 6 cycles, also show all startup and/or cleanup code]

B.2, B.3, B.6

Additional Question (call it 4.EX1):

a) What is the maximum number of physical registers that would be neccessary (for max performance) in a scoreboard machine with explicit register renaming? (ignore the overhead of trying to maintain precise interrupts).
b) Why would the above answer be different if precise interrupts were maintained? How would you estimate the max number of registers in this case?
c) How many total physical registers are available in a Tomasulo architecture that has implicit register renaming? (again ignore the reorder buffer).
Additional Question (call it 4.EX2):

 Consider a string of dependent instructions, i.e. :
      add r1, r2, r3
     sub r4, r1, r2
     add r5, r4, r2
     sub r6, r5, r2,    etc....
Assume that there is a huge (infinite) number of these instructions.  Assume that the adders/subtracters take 1 cycle to execute.

a) What is the best CPI that you could get with a scoreboard (as defined in the book)?
b) What is the best CPI that you could get with a Tomasulo organization (as defined in the book)?
c) Can you fix the Tomasulo architecture so that the above code sequence has a CPI of 1 without increasing the cycletime? (Hint: think in terms of pipelining the wakeup logic in the reservation stations)..

Study groups are encouraged, but pairs should do their own work.
 

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