| 1: | Tiny OS Optimistic Lightweight Interrupt Handler | |
| Simon Yau and Alan Shieh | ||
| TinyOS is a small footprint embeded operating system optimized for space and power. The programming model of TinyOS is a graph of components, which can be implemented in either hardware or software, that communicate with each other through commands and signaling. Software devices are implemented as threads, with very inexpensive context switching on signals. However, signals from hardware typically requires interrupts, which are orders of magnitude more costly than context switches. We aim to decrease the interrupt cost by introducing mechanisms for deferring handling of interrupts and performing as little context switching as possible, while still maintaining real-time constraints. Blah Blah Blah. | ||
| Supporting Documentation: Final Report (ps) | ||
| 2: | Verification architecture | |
| Jaein Jeong and Johnathon Jamison | ||
| As processors get smaller and faster, they become to more vulnerable to transient errors. Minor imperfections in a chip, cosmic rays, or similar phenomenon can cause transistors to occasionally produce wrong results. This does not mean that we cannot use advanced processors because we are afraid of those errors. We can detect those transient errors more stable processors and execute instructions again if an error occurs. If the probability of errors are very low, the overhead of additional verifying processors won't be high. DIVA showed that the idea is feasible. DIVA has a second, slower processor which verifies the output of each individual instruction. We used the idea that we can verify groups of instructions. It is implemented as a dual-processor system with SimpleScalar. A proper system could produce executable programs with no intervention of an operator. Currently, multiple compiler passes and human intervention is required. Our implementation works on a small scale. We believe that the verifying architecture can be applied to a real system with modifications. | ||
| Supporting Documentation: Final Report (pdf) | ||
| 3: | Reduced On-Chip Power Consumption via Data Value Prediction | |
| Alan Chou and Vickie Chan and Lisa Zorn | ||
| As minimum transistor sizes continue to drop below 2 microns and their respective source voltages are reduced well under 2 volts, the power consumption of comparable digital circuits continue to fall. However, the power dissipated by on-chip, metal interconnect is not scaling down as quickly as the transistors themselves--a situation roughly analogous to the Less' Law* gap between memory and processor speed. This study attempts to reduce the power impact of long, on-chip buses via compression schemes adapted from data value prediction techniques, such as last value, stride of n, and context-based data value projections. Of course, the case of no prediction is still reserved. Finally, the benefits of this proposed compression technique are evaluated via simulation of microprocessor bus activity. | ||
| Supporting Documentation: Final Report (pdf) | ||
| 4: | Inter-page Network Resource Sharing Model for SCORE | |
| Norm Zhou and Cathy Huang | ||
| In SCORE an array of on chip reconfigurable compute-pages communicates through streams. On the programming level the page and stream number limitation is abstracted away and taken care of by a compiler and software scheduler. The current SCORE architecture assumes ideal network, i.e. unlimited number of streams per page, with no network congestion and zero communication latency. An inter-compute-page network is needed to implement the streams in hardware. We intend to model ways of constructing such an inter-compute-page network, and analyze tradeoffs involved in cost-performance of different network communication models. In particular we are interested in looking at bandwidth utilization of the physical wires, area cost for implementation, and performance tradeoff between decreased number of pages and buffers, and increased latency. | ||
| Supporting Documentation: Final Report (pdf) | ||
| 5: | Photorealistic Hardware Assistance | |
| Okan Arikan and Tolga Goktekin | ||
| Contemporary computer graphics hardware are built to handle simple rasterization, per fragment operations and geometry for real-time applications. Unfortunately, these hardware can not be used for complicated photorealistic rendering of complex environments for they don't support high level constructs such as complex illumination models (e.g.: raytracing, radiosity) and high quality filtering. These graphics hardware are especially built for real-time applications and such high level constructs can not be implemented in real-time due to their complexities. However, increasing technology and demand for realism motivate integration of such high level operations in hardware. In this project, we will identify the time consuming operations performed in a photorealistic renderer and propose hardware architectures to improve speed. We believe that, such high level hardware assistance will lead to real-time photorealism on future graphics cards. | ||
| Supporting Documentation: Final Report (ps) | ||
| 6: | An Empirical Evaluation of Mote RF Networking (and Beyond...) | |
| Scott Klemmer and Sarah Waterson and Kamin Whitehouse | ||
| Sensing the surroundings of a user can provide a number of contextual cues, enabling the computing environment and applications to tailor their behavior and Context, particularly location, is an important source of information for human-computer interaction. In our project, we examine hardware, networking, and systems issues for a location sensing infrastructure. We present a thorough empirical analysis of the TinyOS RF motes. This analysis is leveraged to build a model of the RF signal strength. We have built a prototype system that employs a Kalman filter to determine distance between pairs of devices. Using a mass-spring system, we aggregate the distance measurements of all the networked devices. The location information is displayed with a visual user interface. | ||
| Supporting Documentation: Final Report (pdf) | ||
| 7: | Quantitative Characterization of Network DoS Attacks | |
| David Bindel and Adam Bargteil and Yan Chen | ||
| As computers are increasingly connected to wide-area networks, network-based denial of service (DoS) attacks are increasingly common. DoS attacks deny access to a service by consuming or destroying a large share of available resources. Theoretical models of DoS attacks as resource allocation problems have been studied for many years, and have been applied to understanding and combatting them, but so far there has been a lack of quantitative characterization of denial of service behaviors. Building on recent work on quantitatively characterizing availability, we plan to characterize resource usage and availability characteristics of the proposed Tapestry routing service under malicious loads. We also plan to investigate solutions to any problems we discover, and perhaps explore some design principles for building DoS-resistant services. | ||
| Supporting Documentation: Final Report (ps) | ||
| 8: | Branch Prediction using Neural Nets | |
| Rupak Majumdar and Dror Weitz | ||
| In this project, we apply introspection to branch prediction. We explore the use of a secondary processor to track the behavior of branches in order to construct models of branch direction patterns and to produce better prediciton tables on the fly. The use of a secondary processor to perform the model construction allows an ambitious combination of software and hardware techniques which is not constrained by traditional resource limitations. | ||
| Supporting Documentation: Final Report (ps) | ||
| 9: | Genetic Algorithms for Bus Protocol and Scheduler Generation | |
| Trevor Meyerowitz and Claudio Pinello | ||
| GA?s (Genetic Algorithms) are useful for exploring a large search space filled with non-obvious possibilities. After seeing the success of using GA?s to construct branch-predictors in , we decided it would be interesting to explore protocol design for mixed sporadic and periodic benchmarks. We want to explore the feasibility of using genetic algorithms to generate bus protocols fit to an expected bus-load. We plan to characterize the bus-load using some message traces.
We aim at generating a hierarchy of schedulers defining how messages should be treated at every communication cycle. | ||
| Supporting Documentation: Final Report (pdf) | ||
| 10: | QoS and Congestion Control on Tapestry | |
| David Liu and Xiaofeng Ren | ||
| Tapestry is a wide-area location/routing layer based on Plaxton trees. The flexible routing mechanism in Tapestry, in particular the incremental routing and the local sibling mesh, enables us to explore the possibility of router-side solutions toward QoS and congestion control. The intuition is that if we are to duplicate packets and send them through different paths ( or, alternatively, use randomized routing ) in the case when local congestion or network failure occurs, the overloaded links or faulty nodes can be circumvented, and guaranteed end-to-end throughput and latency can be achieved. We will compare the performance of our mechanism to TCP/IP by NS2 simulation, and also evaluate its fault tolerance property. | ||
| Supporting Documentation: Final Report (pdf) | ||
| 11: | Building and Measuring a High Performance Network Architecture | |
| Bill Kramer and Members of the SCinet-2000 team | ||
| Once a year, the SC conferences give a unique opportunity to create and build one of the most complex and highest performance networks in the world. Both local and wide area networking connections will be used to demonstrate large scale distributed applications running on different architectures. This project is designed to use this opportunity to create unique test bed environment and then to use that network to demonstrate and evaluate high performance computational and communication applications.
This test bed is designed to incorporate many interoperable systems. It also, is being designed for measurement from the very beginning. The end result will be key insights into how to use novel networking technologies and to accumulate unique measurements that will give insights into the networks of the future. | ||
| Supporting Documentation: Final Report (pdf) | ||