Homework 1 is due Monday September 16 at 5 PM. Turn it in in the appropriate box in 283 Soda. Note that the building is locked (for those who do not have keycard access at 6:45 PM during the week, as well as on the weekends.
Homework assignments should be done in pairs. Each pair is to do their own work, separate from the other pairs. Each pair turns in one solution.
Here are a few simplifications and clarifications regarding question 4.14:
|FP ALU op||anything||3|
For the purposes of the scoreboard and Tomasulo's algorithm, assume that a latency of n cycles implies an execution time of n+1 cycles.
If you already did this problem with the more complex assumptions written in the book, don't worry. Just state what your assumptions are. There's no need to redo any work.
Therefore, given the following instructions:
LD F2,0(R1) ADDD F4,F2,F0and a load latency of 1 (therefore execution time of 2):
In DLX, if the LD issued in cycle 1, the ADDD could issue in cycle 3 (latency of 1 means 1 cycle stall).
in the scoreboard, it would look like so:
|issue||read ops||exec compl||write result|
Any more questions? Feel free to send me mail or use the newsgroup.
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