Two trends call into question the current practice of microprocessors and DRAMs being fabricated as different chips on different fab lines: 1) the gap between processor and DRAM speed is growing at 50% per year; and 2) the size and organization of memory on a single DRAM chip is becoming awkward to use yet size is growing at 60% per year.

Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, improve energy efficiency, and reduce size. Suprisingly, the integration of the processor/cache/memory of IRAM with with high-speed serial I/O lines may also lead to very good I/O performance.

This talk explores some of the opportunities and challenges for IRAMs, suggests that conventional microarchitectures do not exploit IRAM's potential, and proposes an initial architecture that is a better match.

I conclude by speculating on applications for a DRAM-size chip in 2-3 years that consumed 1 watt of power, contained 24 Mbytes of memory, had about 1 Gbyte/sec of I/O, and computed at the rate of 5 GFLOPS (64 bit floating point) and 40 GOPS (8 bit fixed point).

Today, the semiconductor industry is sharply segregated into processor and memory camps. If IRAM proves successful, integration will come to the semiconductor industry. In such a future, will historically DRAM-oriented companies still ship the most memory? Will historically processor-oriented companies still ship the most processors?