Intelligent RAM (IRAM): Chips that remember AND compute

David A. Patterson
U.C. Berkeley

Conventional architectures were developed with a transistor budget
of about 0.1 million transistors and have evolved to designs of about
10 million transistors, often achieving impressive performance in
using 100 times the number of transistors.
However, we believe these architectures will scale not efficiently
another hundredfold to 1 billion transistors.

In this talk we explore a different way of using the huge real 
estate available on such a chip: integrating the processor and 
the main memory on the same die. We call this architecture IRAM, 
for Intelligent RAM.

IRAM merges processing and memory into a single chip to lower memory latency, 
increase memory bandwidth, and improve energy efficiency as
well as to allow more flexible selection of memory size and
organization. In addition, IRAM promises savings in power and board area. 

This talk reviews the state of microprocessors and DRAMs today, explores
some of the opportunities and challenges for IRAMs, estimates performance 
and energy efficiency of IRAM, and discusses pros and cons of initial
IRAM architectures. One initial promising path is a Vector IRAM, which
in Gbit DRAM technology might offer a peak performance of 16 GFLOPS (64 bit) 
and 128 GOPS (8 bit) and 96 MB of storage on a single chip.
(8 bit)-