"Observations on Massively Parallel Processors
a Case for a New Theoretical Model: LogP"

David A. Patterson, Computer Science Division/EECS Dept.
University of California, Berkeley
patterson@cs.berkeley.edu


This talk first predicts the trends in Massively Parallel Processors (MPP) 
from the middle to the end of this decade. MPPs are composed of independent 
technologies that are improving at different rates. To predict the 
future of MPPs, I track the history, current trends, and 
predict the future of these base technologies. These trends are leading
indefatigably towards a common foundation for all MPPs, and are
reflected in recent machines such as the Cray T3D, Intel Paragon, and
Thinking Machines CM-5. These trends are also heading MPPs into a
battle of survival with networks of workstations.

I then compare this common architecture to current theoretical models 
(i.e., PRAM), coming to the surely controversial conclusion that they 
may be too inaccurate to expect them to lead to important contributions 
to MPPs this decade (if ever).  Finally, I conclude the talk with an 
introduction to a more realistic model, called "LogP," developed by 
architects and theoreticians at Berkeley. The name LogP comes from the 
four parameters of the model:

L: Latency of communication in the network.
o: Overhead for the processor to send or receive a message from the network.
g: Gap between consecutive messages sent or received at a processor.
P: number of processor/memory modules.
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This talk was invited to be given at DIMACS Workshop of Models, Architectures,
and Technologies for Parallel Computation, Rutgers, New Jersey
Sept. 20, 1993