The Case for Intelligent RAM (IRAM)

David Patterson, UC Berkeley

5:30 pm, Thursday, January 8, 1998
The Westin Hotel
5101 Great America Pkwy, Santa Clara, California, USA

Will microprocessors and DRAMs continue to be fabricated as different chips on different fab lines? With the gap between processor speed and DRAM speed growing at 50% per year and the size and organization of memory on a single DRAM chip becoming awkward (and the size of DRAMs still growing at 60% per year), is there a better way?

Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, improve energy efficiency, and reduce size. Surprisingly, the integration of the processor/cache/memory of IRAM with high-speed serial I/O lines may also lead to very good I/O performance.

Dr. Patterson, the world leader in IRAM, challenges the industry to consider the possibility that the sharp division between DRAM and processor vendors may disappear. In such a world it is unclear which companies will ship the most memory and which the most processors.

Join us for a provocative evening that looks at the theory behind, and the applications for, IRAM. Dr. Patterson will answer audience questions after his presentation.

David Patterson, professor of computer science at UC Berkeley, has taught computer architecture since joining the faculty in 1977. He has consulted for many companies, including Digital, Hewlett-Packard, Intel, and Sun Microsystems, and is co-author of five books including the fundamental text Computer Architecture: A Quantitative Approach. At Berkeley, he led the design and implementation of RISC I, one of the first VLSI Reduced Instruction Set Computers. This research became the foundation of the SPARC architecture currently used by Sun Microsystems. He was also a leader of the Redundant Arrays of Inexpensive Disks (RAID) project which led to high performance storage systems from many companies.

The $99.00 dinner meeting cost includes all handouts, dinner, wine, and hors d'oeuvres. Seating is limited and advance payment is required to reserve space.

Event Schedule

• 9am-5pm Seminar

• 5:30-6:45pm Reception
  
• 6:45-7:30pm Dinner
  
• 7:30-9:00pm The Case for Intelligent RAM (IRAM)
  

Advance Registration Required

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