WordRev: Finding Word-Level Structures in a Sea of Bit-Level Gates

Wenchao Li, Adria Gascon, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari, Sharad Malik, Natarajan Shankar, and Sanjit A. Seshia. WordRev: Finding Word-Level Structures in a Sea of Bit-Level Gates. In Proceedings of the IEEE Conference on Hardware-Oriented Security and Trust (HOST), June 2013.

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Abstract

Systems are increasingly being constructed from off-the-shelf components acquired through a globally distributed and untrusted supply chain. Often times only post-synthesis gate-level netlists or actual Silicon chips are available for security inspection. This makes reasoning about hardware trojans particularly challenging given the enormous scale of the problem. Currently, there is no methodology that can scope into a bit-level design to allow more comprehensive analysis. In this paper, we present a systematic way of automatically deriving word-level structures from the gate-level netlist of a digital circuit. Our framework is user-friendly --- it allows the user to specify sequences of word-level operations and it can extract the collection of gates corresponding to those operations. We demonstrate the effectiveness of our approach on an SoC comprised of 400,000 IBM 12SOI gates and several open-source designs.

BibTeX

@InProceedings{li-host13,
  author = 	 {Wenchao Li and Adria Gascon and Pramod Subramanyan and Wei Yang Tan and Ashish Tiwari and Sharad Malik and Natarajan Shankar and Sanjit A. Seshia},
  title = 	 {WordRev: Finding Word-Level Structures in a Sea of Bit-Level Gates},
  booktitle = {Proceedings of the IEEE Conference on Hardware-Oriented Security and Trust (HOST)},
  month = {June},
  year = 	 {2013},
  abstract = {Systems are increasingly being constructed from off-the-shelf components acquired through a globally distributed and untrusted supply chain. Often times only post-synthesis gate-level netlists or actual Silicon chips are available for security inspection. This makes reasoning about hardware trojans particularly challenging given the enormous scale of the problem. Currently, there is no methodology that can scope into a bit-level design to allow more comprehensive analysis. In this paper, we present a systematic way of automatically deriving word-level structures from the gate-level netlist of a digital circuit. Our framework is user-friendly --- it allows the user to specify sequences of word-level operations and it can extract the collection of gates corresponding to those operations. We demonstrate the effectiveness of our approach on an SoC comprised of 400,000 IBM 12SOI gates and several open-source designs.},
}