Gate Dielectric Scaling - Integrating Alternative High k Gate Dielectrics
As MOSFETs are scaled beyond the 0.1um
technology node, ultra thin SiO2 gate dielectrics, of less than 20A in
thickness, exhibit significant leakage current (>1A/cm2).
In order to maintain high drive current, while minimizing leakage current,
low equivalent oxide thickness is achieved by using thicker
films of high k gate dielectric. At the present time, the Front
End Processing (FEP) group is focused on the development and the integration
of gate stack technologies which contain alternative high k dielectrics.
The FEP group is a member of the SEMATECH FEP Research Center, a collaboration
between industry and leading semiconductor research universities whose
ultimate mission will be to demonstrate successful gate stack solutions
which meet 50nm roadmap targets. The FEP group will continue the evaluation
of new gate dielectric materials, in the context of both process integration
and device behavior.
Currently, the FEP group is evaluating both near term
gate dielectric candidates (ie., oxynitrides, ultrathin SiO2 and Ta2O5)
in terms of integration and device performance, as well as novel metal
oxide gate dielectrics with significantly higher k for sub 100nm technology.
Specifically, there is an ongoing collaboration with the University of
Texas, Austin to investigate the feasability of both sputtered and CVD
HfO2, ZrO2 and Ta2O5 films. According to thermodynamic calculations, these
oxides form a short list of candidate metal oxides which are stable in
contact with silicon.Hubbard et al. This stability, along with stability
in contact with gate materials (polysilicon, silicon germanium, metal gates)
will be experimentally verified through device fabrication and testing.
As for near term gate dielectric solutions, the FEP group is collaborating
with Applied Materials to investigate novel CVD nitride and oxynitride
processes, as part of the UC-SMART collaboration. Ultimately, the metrics
of interest by which all these dielectrics will be evaluated include interface
stability, thermal stability, process uniformity and defect
morphology/density. Any viable process must also exhibit low density of
interface
traps, excellent leakage performance and reliable transistor action
(good mobility, high drive current, etc).
The MOS process used to fabricate the test structures produces
devices with minimum CD on the order of 0.05um, incorporating LDD
implant and either LOCOS or common source isolation, on epi wafers. In
the FEP process, we are interested in evaluating a variety of gate dielectrics,
as well as in determining which gate stack electrode material is most compatible
with each dielectric.
This work is supported by the Semiconductor
Research Corporation (Award #98-BC-616) through the Center for Research
in Front-End Processes.
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Definitions
-
MOSFET Scaling:
Keeping pace with Moore’s Law requires a geometric increase in transistor
packing density which decreases the area per device. As the critical dimensions
of the transistor decrease, the fabrication and design technology must
evolve to address changes in the physics of devices at the smaller scale.
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to top
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Leakage Current:
Parasitic electron flow from the channel to the gate. Typically, leakage
current is severe for silicon dioxide gate dielectrics < 20A. Back
to top
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Equivalent Oxide Thickness:
A term used to compare various alternative gate dielectrics by the
equivalent amount of oxide which would generate the same amount of capacitance
per unit area. Back to top
-
Front End Processing or FEOL:
The sequence of processes which define the MOS transistor, not including
interconnect and metallization processing. In general, these steps include
isolation, dopant implants, gate stack formation, and junction formation.
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-
Thermal Stability (Budget):
The ability of a material to tolerate high temperature and extended
temperature cycles with respect to chemical changes, mechanical stresses,
and changes in microstructure which could affect device performance. Back
-
Interface Traps:
Surface states located at any conductor (bulk) / insulator (dielectric)
interface which act as donors or acceptors and exist in numbers determined
by the quasi-Fermi level at the interface surface. Back
-
LDD or Lightly Doped Drain Extensions:
A self aligned implantation performed to reduce the energy of electrons
as they approach the drain for the purpose of improving breakdown threshold.
Back
| Alternative High-k Dielectrics |
k |
| SiO2 |
3.5 |
| Si3N4 |
7.0 |
| SixNyOz (Oxynitrides) |
4.0-7.0 |
| Al2O3 |
9 |
| Ta2O5 |
25 |
| ZrO2 |
25 |
| HfO2 |
40 |
| TiO2 |
50 |
| BST (BaSrTiO3) |
300 |
References:
-
Hubbard, K.J.; Schlom, D.G. Thermodynamic stability of binary oxides in
contact with silicon. Journal of Materials Research, vol.11, (no.11), pp.2757-76.
Nov. 1996
-
Song, S. C. et al. Symp. VLSI Tech.. pp. 137-8, 1999 [A novel gate/stack
prepared by RT nitridation and N2O oxidation]
-
Peercy, P. IEDM Tech. Dig. pp. 14-7, 1998 [Scaling current MOS process
technology]
-
Timp, G. IEDM Tech. Dig. pp. 615-8, 1998 [Scaling current MOS process technology]
-
Luan, H. F. IEDM Tech. Dig. pp. 609-611, 1998 [An ultra thin RTP tantalum
pentoxide gate dielectric]
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