PUBLICATIONS

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BOOKS AND JOURNALS EDITED

  1. "Active matrix liquid crystal displays technology and applications," T. Voutsas and T.-J. King, Editors," Proceedings of SPIE -- the International Society for Optical Engineering, Vol. 3014 (SPIE: Bellingham, Washington, USA), ISBN 0-8194-2425-0, 1997.

MAGAZINE ARTICLES

  1. T.-J. King, “Poly-Si TFT technologies for future flat-panel displays,” Information Display, Vol. 17, No. 4, pp. 24-26, 2001.
  2. A. E. Franke, T.-J. King and R. T. Howe, “Integrated MEMS technologies,” MRS Bulletin, Vol. 26, No. 4, pp. 291-295, 2001.
  3. L. Chang, Y.-K. Choi, J. Kedzierski, N. Lindert, P. Xuan, J. Bokor, C. Hu and T.-J. King, “Ultra-thin body SOI and FinFET CMOS transistors for terascale integration,” to appear in IEEE Circuits & Devices, Vol. 19, 2003.

REFEREED JOURNAL PUBLICATIONS

    Regular Papers

  1. T.-J. King, M. G. Hack and I-W. Wu, "Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors," Journal of Applied Physics, Vol. 75, No. 2, pp. 908-913, 1994.
  2. T.-J. King, J. P. McVittie, K. C. Saraswat and J. R. Pfiester, "Electrical properties of heavily doped polycrystalline silicon-germanium films," IEEE Transactions on Electron Devices, Vol. 41, No. 2, pp. 228-232, 1994.
  3. T.-J. King and K. C. Saraswat, "Deposition and properties of low-pressure chemical-vapor deposited polycrystalline silicon-germanium films," Journal of the Electrochemical Society, Vol. 141, No. 8, pp. 2235-2241, 1994.
  4. T.-J. King and K. C. Saraswat, "Polycrystalline silicon-germanium thin-film transistors," IEEE Transactions on Electron Devices, Vol. 41, No. 9, pp. 1581-1591, 1994.
  5. J. D. Bernstein, S. Qin, C. Chan and T.-J. King, "High dose-rate hydrogen passivation of polycrystalline silicon CMOS TFT's by plasma ion implantation," IEEE Transactions on Electron Devices, Vol. 43, No. 11, pp. 1876-1882, 1996.
  6. E. C. Onyiriuka, C. B. Moore, F. P. Fehlner, N. J. Binkowski, D. Salamida, T.-J. King and J. G. Couillard, "Effect of RCA cleaning on the surface chemistry of glass and polysilicon films as studied by ToF-SIMS and XPS," Surface and Interface Analysis, Vol. 26, pp. 270-277, 1998.
  7. B. Yu, D.-H. Ju, W.-C. Lee, N. Kepler, T.-J. King and C. Hu, "Gate engineering for deep-submicron CMOS transistors," IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp. 1253-1262, 1998.
  8. S. Qin, Y. Zhou, T. Nakatsugawa, I. F. Husein, C. Chan and T.-J. King, "Plasma ion implantation hydrogenation of poly-Si CMOS thin-film transistors at low energy and high dose rate using an inductively-coupled plasma source," IEEE Transactions on Electron Devices, Vol. 45, No. 6, pp. 1324-1328, 1998.
  9. S. Yamamichi, A. Yamamichi, D. Park, T.-J. King and C. Hu, “Impact of time dependent dielectric breakdown and stress induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO3 thin film capacitors for Gbit-scale DRAMs,” IEEE Transactions on Electron Devices, Vol. 46, No. 2, pp. 342-347, 1999.
  10. K. L Scott, T.-J. King, K.-N. Leung and M. A. Lieberman, "Pattern generators and microcolumns for ion beam lithography," Journal of Vacuum Science and Technology B, November/December 2000.
  11. D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor and C. Hu, “FinFET -- a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, Vol. 47, No. 12, pp. 2320-2325, 2000.
  12. I. Polishchuk, Q. Lu, Y.-C. Yeo, T.-J. King and C. Hu, “Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET,” IEEE Transactions on Device and Materials Reliability, Vol. 1, No. 1, pp. 4-8, 2001.
  13. Y.-C. King, T.-J. King and C. Hu, "Charge-trap memory device fabricated by oxidation of Si1-xGex," IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 696-700, 2001.
  14. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor and C. Hu, “Sub-50 nm p-channel FinFET,” IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 880-886, 2001.
  15. K. Asano, Y.-K. Choi, T.-J. King and C. Hu, “Patterning sub-30-nm MOSFET gate with i-line lithography,” IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 1004-1006, 2001.
  16. Y.-C. King, C. Kuo, T.-J. King and C. Hu, “Optimization of sub-5-nm multiple-thickness gate oxide formed by oxygen implantation,” IEEE Transactions on Electron Devices, Vol. 48, No. 6, pp. 1279-1281, 2001.
  17. I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King and C. Hu, “Hot-carrier reliability comparison for pMOSFETs with ultrathin silicon-nitride and silicon-oxide gate dielectrics,” IEEE Transactions on Device and Materials Reliability, Vol. 1, No. 3, pp. 158-162, 2001.
  18. K. L Scott, T.-J. King, K.-N. Leung and R. F. Pease, "Characterization of multicusp-plasma ion source brightness using micron-scale apertures," Journal of Vacuum Science and Technology B, Vol. 19, No. 6, pp. 2602-2606, 2001.
  19. J. Reijonen, Q. Ji, T.-J. King, K.N. Leung, A. Persaud and S. Wilde, “Compact focusing system for ion and elecron beams,” Journal of Vacuum Science & Technology B, Vol. 20, No. 1, pp. 180-184, 2002.
  20. Y.-C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor and C. Hu, “Design and fabrication of 50-nm thin-body p-MOSFETS with a SiGe heterostructure channel,” IEEE Transactions on Electron Devices, Vol. 49, No. 2, pp. 279-286, 2002.
  21. Y.-K. Choi, T.-J. King and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp. 436-441, 2002.
  22. P. Ranade, H. Takeuchi, W.-C. Lee, V. Subramanian and T.-J. King, “Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs,” IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1436-1443, 2002.
  23. K. J. Yang, T.-J. King, C. Hu, S. Levy and H. N. Al-Shareef, “Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics,” Solid-State Electronics, Vol. 47, pp. 149-153, 2003.
  24. Y.-C. Jeon, A. Franke, T.-J. King and R. T. Howe, "Properties of Phosphorus-Doped Poly-SiGe Films For MEMS Applications, " to appear in Journal of The Electrochemical Society.
  25. H. Takeuchi and T.-J. King, “Suppression of boron TED (transient enhanced diffusion) by low temperature SPC (solid phase crystallization) anneal prior to dopant activation,” to appear in IEEE Transactions on Electron Devices, Vol. 49, 2002.
  26. Y. Cao, R. A. Groves, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, X. Huang, T.-J. King and C. Hu, “Frequency independent equivalent circuit model for on-chip spiral inductors,” to appear in IEEE Journal of Solid-State Circuits.
  27. X. Huang, P. Restle, T. Bucelot, Y. Cao, T.-J. King and C. Hu, “Loop-Based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design,” to appear in IEEE Journal of Solid-State Circuits.
  28. L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu and T.-J. King, “Extremely scaled silicon nano-CMOS devices,” to appear in Proceedings of the IEEE.

    29. Letters and Briefs

  29. T.-J. King, J. R. Pfiester and K. C. Saraswat, "A variable-work-function polycrystalline-Si1-xGex gate material for submicrometer CMOS technologies," IEEE Electron Device Letters, Vol. 12, No. 10, pp. 533-535, 1991.
  30. T.-J. King, K. C. Saraswat and J. R. Pfiester, "PMOS transistors in LPCVD polycrystalline silicon-germanium films," IEEE Electron Device Letters, Vol. 12, No. 11, pp. 584-586, 1991.
  31. T.-J. King and K. C. Saraswat, "Low-temperature (<550oC) fabrication of poly-Si thin-film transistors," IEEE Electron Device Letters, Vol. 13, No. 6, pp. 309-311, 1992.
  32. M. Cao, T.-J. King and K. C. Saraswat, "Determination of the densities of gap states in hydrogenated polycrystalline Si and Si0.8Ge0.2 films," Applied Physics Letters, Vol. 61, No. 6, pp. 672-674, 1992.
  33. S. Jurichich, T.-J. King, K.C. Saraswat and J. Mehlhaff, "Low thermal budget polycrystalline silicon-germanium thin-film transistors fabricated by rapid thermal annealing," Japanese Journal of Applied Physics, Vol. 33, No. 8, pp. L1139-L1141, 1994.
  34. D. S. Bang, M. Cao, A. Wang, K. C. Saraswat and T.-J. King, "Resistivity of boron and phosphorus doped polycrystalline Si1-xGex films," Applied Physics Letters, Vol. 66, No. 2, pp. 195-197, 1995.
  35. J. D. Bernstein, S. Qin, C. Chan and T.-J. King, "Hydrogenation of polycrystalline silicon thin film transistors by plasma ion implantation," IEEE Electron Device Letters, Vol. 16, No. 10, pp. 421-423, 1995.
  36. B. Yu, D.-H. Ju, N. Kepler, T.-J. King and C. Hu, "Impact of Gate Microstructure on Complementary Metal-Oxide-Semiconductor Transistor Performance," Japanese Journal of Applied Physics Part 2, Letters, Vol. 36, No. 9AB, pp. L1150-L1152, 1997.
  37. W.-C. Lee, Y.-C. King, T.-J. King and C. Hu, "Observation of reduced poly-gate depletion effect for poly-Si0.8Ge0.2-gate NMOS devices," Electrochemical and Solid State Letters, Vol. 1, No. 1, pp. 58-59, 1998.
  38. W.-C. Lee, T.-J. King and C. Hu, "Investigation of poly-Si1-xGex for dual gate CMOS technology," IEEE Electron Device Letters, Vol. 19, No. 7, pp. 247-249, 1998.
  39. Q. Lu, D. Park, A. Kalnitsky, C. Chang, C.-C. Cheng, S. P. Tay, T.-J. King and C. Hu, "Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics," IEEE Electron Device Letters, Vol. 19, No. 9, pp. 341-342, 1998.
  40. D. Park, Y.-C. King, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay and C.-C. Cheng, "Transistor characteristics with Ta2O5 gate dielectric," IEEE Electron Device Letters, Vol. 19, No. 11, pp. 441-443, 1998.
  41. W.-C. Lee, T.-J. King and C. Hu, , “Observation of reduced boron penetration and poly-gate depletion for poly-Si0.8Ge0.2-gated PMOS devices,” IEEE Electron Device Letters, Vol. 20, No. 1, pp. 9-11, 1999.
  42. W.-C. Lee, B. Watson, T.-J. King, and C. Hu, “Enhancement of PMOS device performance with poly-SiGe Gate,” IEEE Electron Device Letters, Vol. 20, No. 5, pp. 232-234, 1999.
  43. W.-C. Lee, T.-J. King and C. Hu, “Evidence of direct hole tunneling through ultrathin gate oxide using P+ poly-SiGe gate,” IEEE Electron Device Letters, Vol. 20, No. 6, pp. 268-270, 1999.
  44. Y.-J. Tung, J. Boyce, J. Ho, X. Huang and T.-J. King, “A comparison of hydrogen and deuterium plasma treatment effects on polysilicon TFT performance and DC reliability,” IEEE Electron Device Letters, Vol. 20, No. 8, pp. 387-389, 1999.
  45. Y.-C. King, T.-J. King and C. Hu, “A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide,” IEEE Electron Device Letters, Vol. 20, No. 8, pp. 409-411, 1999.
  46. Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor and C. Hu, “Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel,” IEEE Electron Device Letters, Vol. 21, No. 4, pp. 161-163, 2000.
  47. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor and C. Hu, “Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron Device Letters, Vol. 21, No. 5, pp. 254-255, 2000.
  48. Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo and T.P. Ma, “Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Letters, Vol. 21, No. 11, pp. 540-542, 2000.
  49. Y. C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan and D.-L. Kwong, “Dual metal gate CMOS technology with ultrathin silicon nitride gate dielectric,” IEEE Electron Device Letters, Vol. 22, No. 5, pp. 227-229, 2001.
  50. Q. Lu, Y. C. Yeo, K. J. Yang, R. Lin, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, X. Guo, Z. Luo, X. Wang and T.-P. Ma, “Two silicon nitride technologies for post-SiO2 MOSFET gate dielectric,” IEEE Electron Device Letters, Vol. 22, No. 7, pp. 324-326, 2001.
  51. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, “Dual work function metal gate CMOS technology using metal interdiffusion,” IEEE Electron Device Letters, Vol. 22, No. 9, pp. 444-446, 2001.
  52. Y.-K. Choi, D. Ha, T.-J. King, and C. Hu, “Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain,” IEEE Electron Device Letters, Vol. 22, No. 9, pp. 447-448, 2001.
  53. N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor and C. Hu, “Sub-60-nm quasi-planar FinFETs fabricated using a simplified process,” IEEE Electron Device Letters, Vol. 22, No. 10, pp. 487-489, 2001.
  54. P. Ranade, H. Takeuchi, T.-J. King and C. Hu, “Work function engineering of molybdenum gate electrodes by nitrogen implantation,” Electrochemical and Solid-State Letters, Vol. 4, No. 11, pp. G85-G87, 2001.
  55. Y.-K. Choi, T.-J. King and C. Hu, “Nanoscale CMOS spacer FinFET for the terabit era,” IEEE Electron Device Letters, Vol. 23, No. 1, pp. 25-27, 2002.
  56. P. Ranade, H. Takeuchi, V. Subramanian and T.-J. King, “Observation of Boron and Arsenic mediated interdiffusion across Germanium/Silicon interfaces,” Electrochemical and Solid-State Letters, Vol. 5, No. 2, pp. G5-G7, 2002.
  57. R. Lin, Q. Lu, P. Ranade, T.-J. King and C. Hu, “An adjustable work function technology using Mo gate for CMOS devices,” IEEE Electron Device Letters, Vol. 23, No. 1, pp. 49-51, 2002.
  58. M. She, T.-J. King, C. Hu, W. Zhu, Z. Luo, J.-P. Han, T.-P. Ma, “JVD silicon nitride as tunnel dielectric in p-channel flash memory,” IEEE Electron Device Letters, Vol. 23, No. 2, pp. 91-93, 2002.
  59. I. Polishchuk P. Ranade, T.-J. King and C. Hu, “Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion,” IEEE Electron Device Letters, Vol. 23, No. 4, pp. 200-202, 2002.
  60. P. Ranade, H. Takeuchi, V. Subramanian and T.-J. King, “A novel elevated source/drain PMOSFET formed by Ge-B/Si intermixing,” IEEE Electron Device Letters, Vol. 23, No. 4, pp. 218-220, 2002.
  61. H. Takeuchi, P. Ranade, V. Subramanian and T.-J. King, “Observation of dopant-mediated intermixing at Ge/Si interface,” Applied Physics Letters, Vol. 80, No. 20, pp. 3706-3708, May 2002.
  62. Y.-C. Yeo, P. Ranade, T.-J. King and C. Hu, “Effects of high-k gate dielectric materials on metal and silicon gate workfunctions,” IEEE Electron Device Letters, Vol. 23, No. 6, pp. 342-344, 2002.
  63. C. Kuo, T.-J. King and C. Hu, “A capacitorless double-gate DRAM cell,” IEEE Electron Device Letters, Vol. 23, No. 6, pp. 345-347, 2002.

CONFERENCE PRESENTATIONS/PAPERS

    Refereed:

  1. T.-J. King, J. R. Pfiester, J. D. Shott, J. P. McVittie and K. C. Saraswat, “A polycrystalline-Si1-xGex-gate CMOS technology,” International Electron Devices Meeting Technical Digest, pp. 253-256, 1990.
  2. T.-J. King and K. C. Saraswat, “A low-temperature (<550oC) silicon-germanium MOS thin-film transistor technology for large-area electronics,” International Electron Devices Meeting Technical Digest, pp. 567-570, 1991.
  3. M. Hack, I-W. Wu, A. G. Lewis and T.-J. King, “Numerical simulations of poly-crystalline silicon thin film transistors including leakage effects,” IEE Colloquium on Poly-Si Devices and Applications, IEE Digest No. 1993/067, pp. 23/1-23/4, 1993.
  4. M. Hack, I-W. Wu, A. Lewis and T.-J. King, “Numerical simulations of ON and OFF state characteristics of poly-silicon thin film transistors,” IEEE Transactions on Electron Devices, Vol. 40, No. 11, p. 2128, 1993 (presented at the 51st Annual Device Research Conference).
  5. S. Jurichich, T.-J. King, K. Saraswat and J. Mehlhaff, “A low-thermal-budget polycrystalline silicon-germanium thin-film transistor technology for large-area electronics,” Proceedings of International Semiconductor Device Research Symposium, pp. 55-58, 1993.
  6. M. Hack, I-W. Wu, T.-J. King and A. G. Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” International Electron Devices Meeting Technical Digest, pp. 385-388, 1993.
  7. T.-J. King and M. Hack, “Two-dimensional drain engineering for leakage reduction in thin-film transistors,” 52nd Annual Device Research Conference Digest, p. IIIA-5, 1994.
  8. J. D. Bernstein, S. Qin, C. Chan and T.-J. King, “A study of process conditions for plasma ion implantation hydrogenation experiments,” presented at the IEEE International Conference on Plasma Science (Madison, Wisconsin, USA), June 1995.
  9. E. Cheng, J. C. Sturm, I-W. Wu and T.-J. King, “Modeling of leakage current distributions in series connected polysilicon thin film transistors,” Proceedings of 2nd International Workshop on Active Matrix Liquid Crystal Displays, pp. 102-105, 1995.
  10. A. J. Tang, J. A. Tsai, R. Reif and T.-J. King, “A novel poly-Si-capped poly-Si1-xGex thin-film transistor,” International Electron Devices Meeting Technical Digest, pp. 513-516, 1995.
  11. H. Y. Tong, T.-J. King and F. G. Shi, “Crystallization of amorphous SiGe thin films,” Thin Solid Films, Vol. 290-291, pp. 464-468, 1996 (presented at the International Conference on Metallurgical Coatings and Thin Films (San Diego, California, USA), April 1996).
  12. V. Suntharalingam, S. J. Fonash and T.-J. King, “A comprehensive study of the electrical stress stability of n-channel poly-Si TFTs,” Proceedings of the SID 16th International Display Research Conference, pp. 283-285, 1996.
  13. B. Yu, D.-H. Ju, N. Kepler, T.-J. King and C. Hu, “Gate engineering for performance and reliability in deep-submicron CMOS technology,” Symposium on VLSI Technology Digest of Technical Papers, pp. 105-106, 1997.
  14. B. Yu, T.-J. King, C. Hu, D.-H. Ju and N. Kepler, “CMOS transistor reliability and performance impacted by gate microstructure,” IEEE International Integrated Reliability Workshop Final Report, pp. 35-41, 1997.
  15. Best Student Paper: W.-C. Lee, A. Wang, T.-J. King and C. Hu, “Impact of poly-Si0.8Ge0.2-gate technology on device performance and reliability,” Proceedings of the 1997 International Semiconductor Device Research Symposium, pp. 513-516, 1997.
  16. B. Yu, Y.-J. Tung, S. Tang, E. Hui, T.-J. King and C. Hu, “Ultra-thin-body silicon-on-insulator MOSFET’s for terabit-scale integration,” Proceedings of the 1997 International Semiconductor Device Research Symposium, pp. 623-626, 1997.
  17. Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, X. Meng, R. Weiss, G. A. Davis, V. Aebi and T.-J. King, “An ultra-low-temperature-fabricated poly-Si TFT with stacked composite ECR-PECVD gate oxide,” SID International Symposium Digest of Technical Papers, Vol. 29, pp. 887-890, 1998.
  18. D. Park, M. Kennard, Y. Melaku, N. Benjamin, T.-J. King and C. Hu, “Stress-induced leakage current due to charging damage: gate oxide thickness and gate poly-Si etching condition dependence,” Proceedings of the 1998 3rd International Symposium on Plasma Process-Induced Damage, pp. 56-59, 1998.
  19. W.-C. Lee, T.-J. King and C. Hu, “Optimized poly-Si1-xGex-gate technology for dual gate CMOS application,” Symposium on VLSI Technology Digest of Technical Papers, pp. 190-191, 1998.
  20. Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, X. Meng, R. Weiss, G. A. Davis, V. Aebi and T.-J. King, “A high-performance poly-Si TFT technology compatible with flexible plastic substrates,” presented at the 56th Annual Device Research Conference (Charlottesville, Virginia, USA), June 1998.
  21. Y.-J. Tung, J. Boyce, J. Ho, X. Huang and T.-J. King, “A comparative study of hydrogen and deuterium plasma treatment effects on the performance and reliability of polysilicon TFTs,” presented at the 56th Annual Device Research Conference (Charlottesville, Virginia, USA), June 1998.
  22. Y.-C. King, T.-J. King and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex,” International Electron Devices Meeting Technical Digest, pp. 115-118, 1998.
  23. S. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T. W. Sigmon, Y.-J. Tung and T.-J. King, “Polysilicon thin film transistors fabricated at 100oC on a flexible plastic substrate,” International Electron Devices Meeting Technical Digest, pp. 257-260, 1998.
  24. D. Park, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay and C.-C. Cheng, “SiON/Ta2O5/TiN gate stack transistor with 1.8 nm equivalent SiO2 thickness,” International Electron Devices Meeting Technical Digest, pp. 381-384, 1998.
  25. M. Krishnan, Y.-C. Yeo, Q. Lu, T.-J. King, J. Bokor and C. Hu, “Remote charge scattering in MOSFETs with ultra-thin gate dielectrics,” International Electron Devices Meeting Technical Digest, pp. 571-574, 1998.
  26. Y.-C. King, C. Kuo, T.-J. King and C. Hu, “Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation,” International Electron Devices Meeting Technical Digest, pp. 585-588, 1998.
  27. D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K. Asano, T.-J. King, J. Bokor and C. Hu, “A folded-channel MOSFET for deep-sub-tenth micron era,” International Electron Devices Meeting Technical Digest, pp. 1032-1034, 1998.
  28. A. E. Franke, D. T. Chang, P. T. Jones, T.-J. King, R. T. Howe and G. C. Johnson, “Post-CMOS integration of germanium microstructures,” Twelfth IEEE International Conference on Micro Electro Mechanical Systems, pp. 630-637, 1999.
  29. Y.-J. Tung, J. Ho, J. Boyce, X. Huang and T.-J. King, “Improved DC reliability of polysilicon thin-film transistors with deuterium plasma treatment,” SID International Symposium Digest of Technical Papers, pp. 398-401, 1999.
  30. J. M. Heck, Chris G. Keller, A. E. Franke, Lilac Muller, R. T. Howe and T.-J. King, “High aspect ratio poly-silicon-germanium microstructures,” in Proceedings of the 1999 International Conference on Solid-State Sensors and Actuators -- Transducers ‘99 (Sendai, Japan), pp. 328-331, 1999.
  31. A. E. Franke, D. Bilic, D. T. Chang, P. T. Jones, T.-J. King, R. T. Howe and G. C. Johnson, “Optimization of poly-silicon-germanium as a microstructural material,” in Proceedings of the 1999 International Conference on Solid-State Sensors and Actuators -- Transducers ‘99 (Sendai, Japan), pp. 530-533, 1999.
  32. V. Subramanian, J. Kedzierski, N. Lindert, H. Tam, Y. Su, J. McHale, K. Cao, T.-J. King, J. Bokor and C. Hu, “A bulk-Si-compatible ultrathin-body SOI technology for sub-100 nm MOSFETs,” 57th Annual Device Research Conference Digest, pp. 28-29, 1999.
  33. W.-C. Lee, T.-J. King and C. Hu, “Performance enhancement in deep-submicron poly-SiGe-gated CMOS devices,” 1999 International Symposium on VLSI Technology, Systems, and Applications, Proceedings of Technical Papers, pp. 14-18, 1999.
  34. Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor and C. Hu, “Nanoscale SiGe-channel ultra-thin-body silicon-on-insulator P-MOSFETs,” 1999 International Semiconductor Device Research Symposium Proceedings, pp. 295-298, 1999.
  35. Q. Lu, Y. C. Yeo, K. Yang, R. Lin, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, X. Guo, X. Wang, T.-P. Ma, “Comparison of 14A Tox,eq JVD and RTCVD silicon nitride gate dielectrics for sub-100 nm MOSFETs,” International Semiconductor Device Research Symposium Proceedings, pp. 489-492, 1999.
  36. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor and C. Hu, “Sub 50-nm FinFET: PMOS,” International Electron Devices Meeting Technical Digest, pp. 67-70, 1999.
  37. M. S. Krishnan, L. Chang, T.-J. King, J. Bokor and C. Hu, “MOSFETs with 9 to 13A Thick Gate Oxides,” International Electron Devices Meeting Technical Digest, pp. 241-244, 1999.
  38. H. Takeuchi, W.-C. Lee, P. Ranade and T.-J. King, “Improved PMOSFET short-channel performance using ultra-shallow Si0.8Ge0.2 source/drain extensions,” International Electron Devices Meeting Technical Digest, pp. 501-504, 1999.
  39. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor and C. Hu, “Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” International Electron Devices Meeting Technical Digest, pp. 919-921, 1999.
  40. Q. Ji, T.-J. King, Y. Y. Lee and K.-N. Leung, “Maskless direct-write lithography using focused O2+ beam,” presented at the 44th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Palm Springs, California, USA), June 2000.
  41. K. L. Scott, T.-J. King and K.-N. Leung, “Microfabrication of pattern generators and microcolumns for ion beam lithography,” presented at the 44th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Palm Springs, California, USA), June 2000.
  42. A. E. Franke, Y. Jiao, M. T. Wu, T.-J. King and R. T. Howe, “Post-CMOS modular integration of poly-SiGe microstructures using poly-Ge sacrificial layers,” Solid-State Sensor and Actuator Workshop Technical Digest, pp. 18-21, June 2000.
  43. Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor and C. Hu, “30nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D,” 58th Annual Device Research Conference Digest, pp. 23-24, 2000.
  44. Y. C. Yeo, Q. Lu, W.-C. Lee, T.-J. King and C. Hu, “Scaling limit of silicon nitride gate dielectric for future CMOS technologies,” 58th Annual Device Research Conference Digest, pp. 65-66, 2000.
  45. P. Xuan, J. Kedzierski, V. Subramanian, J. Bokor, T.-J. King and C. Hu, “60nm planarized ultra-thin body solid phase epitaxy MOSFETs,” 58th Annual Device Research Conference Digest, pp. 67-68, 2000.
  46. J. Kedzierski, P. Xuan, V. Subramanian, J. Bokor, T.-J. King, C. Hu, and E. A. Anderson, “20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain,” Superlattices and Microstructures, Vol.28, No.5-6, p.445-52, 2000 (presented at the 5th Silicon Nanoelectronics Workshop, Honolulu, HI, USA, 11-12 June 2000.)
  47. Q. Lu, Y. C. Yeo, P. Ranade, H. Takeuchi, T.-J. King and C. Hu, “Dual-metal gate technology for deep-submicron CMOS transistors,” Symposium on VLSI Technology, Digest of Technical Papers, pp. 72-73, 2000.
  48. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King and C. Hu, "Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime,” International Electron Devices Meeting Technical Digest, pp. 57-60, 2000.
  49. Q. Lu, R. Lin, P. Ranade, Y. C. Yeo, X. Meng, H. Takeuchi, T.-J. King, C. Hu, H. Luan, S. Lee, W. Bai, C.-H. Lee, D.-L. Kwong, X. Guo, X. Wang and T.-P. Ma, “Molybdenum metal gate MOS technology for post-SiO2 gate dielectrics,” International Electron Devices Meeting Technical Digest, pp. 641-644, 2000.
  50. L. Chang, S. Tang, T.-J. King, J. Bokor and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs,” International Electron Devices Meeting Technical Digest, pp. 719-722, 2000.
  51. X. Huang, Y. Cao, D. Sylvester, S. Lin, T.-J. King and C. Hu, "RLC signal integrity analysis of high-speed global interconnect,” International Electron Devices Meeting Technical Digest, pp. 731-734, 2000.
  52. Y.-C. Yeo, Q. Lu, T.-J. King, C. Hu, T. Kawashima, M. Oishi, S. Mashiro and J. Sakai, "Enhanced performance in sub-100nm CMOSFETs using strained epitaxial silicon-germanium,” International Electron Devices Meeting Technical Digest, pp. 753-756, 2000.
  53. S. H. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King and C. Hu, “FinFET -- a quasi-planar double-gate MOSFET,” presented at the International Solid-State Circuits Conference (San Francisco, California, USA), February 2001.
  54. I. Polishchuk, Y.-C. Yeo, Q. Lu, T.-J. King and C. Hu, "Hot-carrier reliability of P-MOSFET with ultra-thin silicon nitride gate dielectric,” presented at the International Reliability Physics Symposium (Orlando, Florida, USA), April 2001.
  55. J. Reijonen, Q. Ji, T.-J. King, K.-N. Leung, A. Persaud and S. Wilde, “Compact focusing system for ion and electron beams,” presented at the 45th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Washington, D.C., USA), May 2001.
  56. K. L. Scott, T.-J. King, K.-N. Leung and R. F. Pease, “Characterization of multicusp-plasma ion source brightness using micron-scale apertures,” presented at the 45th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Washington, D.C., USA), May 2001.
  57. Y.-K. Choi, D. Ha, T.-J. King and C. Hu, “Ultra-thin body PMOSFETs with selectively deposited Ge source/drain,”  presented at the 2001 Symposium on VLSI Technology (Kyoto, Japan), June 2001.
  58. Q. Lu, R. Lin, P. Ranade, T.-J. King and C. Hu, “Metal gate work function adjustment for future CMOS technology,”  presented at the 2001 Symposium on VLSI Technology (Kyoto, Japan), June 2001.
  59. Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King and C. Hu, “Effects of high-k dielectrics on the workfunctions of metal and silicon gates,” presented at the 2001 Symposium on VLSI Technology (Kyoto, Japan), June 2001.
  60. I. Polishchuk, T.-J. King and C. Hu, “Physical origin of SILC and noisy breakdown in very thin silicon nitride gate dielectric,” presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
  61. N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor and C. Hu, “Quasi-planar NMOS FinFETs with sub-100nm gate lengths,” presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
  62. Y.-K. Choi, D. Ha, T.-J. King and C. Hu, “Threshold voltage shift by quantum confinement in ultra-thin body device,”  presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
  63. M. She, Y.-C. King, T.-J. King and C. Hu, “Modeling and design study of nanocrystal memory devices,” presented at the 59th Annual Device Research Conference (Notre Dame, Indiana, USA), June 2001.
  64. J. Kedzierski, M. Ieong, P. Xuan, J. Bokor, T.-J. King and C. Hu, “Design analysis of thin-body silicide source/drain devices,” 2001 IEEE International SOI Conference Proceedings, pp. 21-22, 2001.
  65. N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, T.-J. King, J. Bokor and C. Hu, “Quasi-planar FinFETs with selectively grown germanium raised source/drain,” 2001 IEEE International SOI Conference Proceedings, pp. 111-112, 2001.
  66. L. Chang, K. J. Yang, Y.-C. Yeo, Y.-K. Choi, T.-J. King and C. Hu, "Reduction of direct-tunneling gate leakage current in double-gate and ultra-thin body MOSFETs,” International Electron Devices Meeting Technical Digest, pp. 99-102, 2001.
  67. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor and C. Hu, "Sub-20nm CMOS FinFET technologies,” International Electron Devices Meeting Technical Digest, pp. 421-424, 2001.
  68. Q. Lu, R. Lin, H. Takeuchi, T.-J. King, C. Hu, K. Onishi, R. Choi, C.-S. Kang and J. C. Lee, “Deep-submicron CMOS process integration of HfO2 gate dielectric with poly-Si gate,” 2001 International Semiconductor Device Research Symposium Proceedings, pp. 377-380, 2001.
  69. I. Polishchuk, P. Ranade, T.-J. King and C. Hu, “Dual work function metal gate CMOS transistors fabricated by Ni-Ti interdiffusion,” 2001 International Semiconductor Device Research Symposium Proceedings, pp. 411-415, 2001.
  70. 2nd Best Student Paper: Y.-K. Choi, T.-J. King and C. Hu, “Spacer FinFET: Nano-scale CMOS technology for the terabit era,” 2001 International Semiconductor Device Research Symposium Proceedings, pp. 543-546, 2001.
  71. M. She, T.-J. King, C. Hu, W. Zhu, Z. Luo, J.-P. Han and T.-P. Ma, “Low-voltage, fast-programming p-channel flash memory with JVD tunneling nitride,” 2001 International Semiconductor Device Research Symposium Proceedings, pp. 641-644, 2001.
  72. Q. Lu, T.-J. King, C. Hu, “Hot carrier reliability of n-MOSFET with ultra-thin HfO2 gate dielectric and poly-Si gate,”  presented at the International Reliability Physics Symposium (Dallas, Texas, USA), April 2002.
  73. X. Huang, P. Restle, T. Bucelot, Y. Cao and T.-J. King, "Loop-based interconnect modeling and optimization approach for multi-GHz clock network design,” presented at the Custom Integrated Circuits Conference (Orlando, Florida, USA), May 2002.
  74. Y. Cao, R. A. Groves, N. D. Zamdmer, J.-O. Plouchart, R. A. Wachnik, X. Huang, T.-J. King and C. Hu, "Frequency-independent equivalent circuit model for on-chip spiral inductors,” presented at the Custom Integrated Circuits Conference (Orlando, Florida, USA), May 2002.
  75. Q. Ji, X. Jiang, T.-J. King, K.-N. Leung and K. Standiford, “Improvement of brightness for multicusp-plasma ion source,” presented at the 46th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication (Anaheim, California, USA), May 2002.
  76. S. A. Bhave, B. L. Bircumshaw, W. Z. Low, Y.-S. Kim, T.-J. King, R. T. Howe and A. P. Pisano, “Poly-SiGe: A high-Q structural material for integrated RF MEMS,” Solid-State Sensor and Actuator Workshop, Technical Digest,pp. 34-37, 2002.
  77. Q. Lu, H. Takeuchi, X. Meng, T.-J. King, C. Hu, K. Onishi, H.-J. Cho and J. Lee, “Improved performance of ultra-thin HfO2 CMOSFETs using poly-SiGe gate,” presented at the 2002 VLSI Symposium on Technology (Honolulu, Hawaii, USA), June 2002.
  78. I. Polishchuk, K. J. Yang, T.-J. King and C. Hu, “Improved MOSFET electron mobility for advanced gate dielectric stacks,”  60th Annual Device Research Conference, Conference Digest, pp. 75-76, 2002.
  79. I. Polishchuk, Y.-C. Yeo, T.-J. King and C. Hu, “Tunneling through multi-layer gate dielectrics - an analytical model,”  60th Annual Device Research Conference, Conference Digest, pp. 105-106, 2002.
  80. Y.-K. Choi, D. Ha, T.-J. King and J. Bokor, "Reduction of Gate-Induced Drain Leakage (GIDL) Current in Single-Gate Ultra-Thin Body and Double-Gate FinFET Devices," presented at the 2002 International Conference on Solid State Devices and Materials (Nagoya, Japan), September 2002.
  81. D. Ha, P. Ranade, Y.-K. Choi, J.-S. Lee, T.-J. King and C. Hu, "Ultra Thin Body Silicon-On-Insulator (UTB SOI) MOSFET with Metal Gate Work-function Engineering for Sub-70nm Technology Node," presented at the 2002 International Conference on Solid State Devices and Materials (Nagoya, Japan), September 2002.
  82. K.-J. Yang, H. Takeuchi, T.-J. King and C. Hu, "Frequency Dependence of Capacitance Measurement for Advanced Gate Dielectrics," presented at the 2002 International Conference on Solid State Devices and Materials (Nagoya, Japan), September 2002.
  83. Y. Cao, X. Huang, D. Sylvester, T.-J. King and C. Hu, "Impact of On-Chip Interconnect Frequency-Dependent R(f)L(f) on Digital and RF Design," presented at the 15th Annual IEEE International ASIC/SOC Conference (Rochester, New York, USA), September 2002.
  84. X. Huang, Y. Cao, T.-J. King and C. Hu, "Analytical Performance Models for RLC Interconnects and Application to Clock Optimization," presented at the 15th Annual IEEE International ASIC/SOC Conference (Rochester, New York, USA), September 2002.
  85. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, T.-J. King, J. Bokor, M.-R. Lin and D. Kyser, "FinFET Scaling: Towards 10nm Gate Length," International Electron Devices Meeting Technical Digest, pp. 251-254, 2002.
  86. Y.-K. Choi, L. Chang, P. Ranade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, T.-J. King and J. Bokor "FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering," International Electron Devices Meeting Technical Digest, pp. 259-262, 2002.
  87. P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen and T.-J. King, "Tunable-Work-Function Molybdenum Gate Technology for FDSOI-CMOS," International Electron Devices Meeting Technical Digest, pp. 363-366, December 2002.
  88. C. Kuo, T.-J. King and C. Hu, "A Capacitorless Double-Gate DRAM Cell Design for High Density Applications," International Electron Devices Meeting Technical Digest, pp. 843-846, 2002.
  89. H. Takeuchi, P. Ranade and T.-J. King, “Low-temperature dopant activation technology using elevated Ge-S/D structure,” to be presented at the First International SiGe Technology and Device Meeting (Nagoya, Japan), January 2003.
  90. M. She and T.-J. King, “Improved SONOS-type flash memory using HfO2 as trapping layer,” to be presented at the 19th IEEE Non-Volatile Semiconductor Memory Workshop (Monterey, California, USA), February 2003.
  91. R. Yamada and T.-J. King, “Variable stress-induced leakage current and analysis of anomalous charge loss for flash memory application,” to be presented at the IEEE International Reliability Physics Symposium (Dallas, Texas, USA), April 2003.
  92. S. Balasubramanian, L. Chang, Y.-K. Choi, D. Ha, J. Lee, P. Ranade, S. Xiong, J. Bokor, C. Hu and T.-J. King, “Extremely scaled ultra-thin-body and FinFET CMOS devices,” to be presented at the 11th International Symposium on SOI Device Technologies (Symposium J3, 203rd Meeting of the Electrochemical Society, Paris, France), April 2003.

    93. Non-Refereed:

  93. S. Wood, P. Apte, T.-J. King, M. Moslehi and K. Saraswat, “Pyrometer modeling for rapid thermal processing,” Proceedings of the SPIE --The International Society of Optical Engineering, Vol. 1393, pp. 337-348, 1990.
  94. Invited Paper: I-W. Wu, T.-J. King, M. Hack, C. C. Tsai, A. G. Lewis and A. Chiang, “Leakage currents in polycrystalline silicon thin film transistors for liquid crystal displays,” Proceedings of International Semiconductor Device Research Symposium, pp. 21-24, 1993.
  95. Invited Paper: T.-J. King, “Trends in polycrystalline-silicon thin-film transistor technologies for AMLCDs,” Proceedings of 2nd International Workshop on Active Matrix Liquid Crystal Displays, pp. 80-86, 1995.
  96. S. Qin, J. D. Bernstein, Y. Zhou, W. Liu, C. Chan and T.-J. King, “Short-time hydrogen passivation of poly-Si CMOS thin film transistors by high dose rate plasma ion implantation,” Ion-Solid Interactions for Materials Modifications and Processing, MRS Symposium Proceedings Vol. 396, pp. 515-520, 1995 (presented at the MRS 1995 Fall Meeting).
  97. L. M. Lust, T.-J. King, I-W. Wu and W. B. Jackson, “Telegraph noise as a probe of defects in thin film transistors,” presented at the MRS 1996 Spring Meeting (San Francisco, California, USA), April 1996.
  98. V. Suntharalingam, S. J. Fonash and T.-J. King, “A comprehensive study of the electrical stress stability of n-channel poly-Si TFTs,” Proceedings of the Third Symposium on Thin Film Transistor Technologies (presented at the ECS 1996 Fall Meeting, San Antonio, Texas, USA), pp. 260-268, 1997.
  99. K. C. Saraswat, S. Jurichich, T.-J. King, V. Subramanian and A. Wang, “A low temperature polycrystalline SiGe CMOS TFT technology for large area AMLCD drivers,” Proceedings of the Third Symposium on Thin Film Transistor Technologies (presented at the ECS 1996 Fall Meeting, San Antonio, Texas, USA), pp. 186-196, 1997.
  100. Y. Zhou, S. Qin, C. Chan and T.-J. King, “Investigation of plasma immersion ion implantation hydrogenation for poly-Si TFTs using an ICP plasma source,” presented at the MRS 1996 Fall Meeting (Boston, Massachusetts, USA), December 1996.
  101. Invited Paper: C. Chan, S. Qin and T.-J. King, “Plasma ion implantation for flat panel displays,” presented at the MRS 1996 Fall Meeting (Boston, Massachusetts, USA), December 1996.
  102. H. Y. Tong, Q. Jiang, D. Hsu, T.-J. King and F. G. Shi, “Microstructural evolution of amorphous Si1-xGex thin films,” Polycrystalline Thin Films -- Structure, Texture, Properties and Applications III (presented at the MRS 1997 Spring Meeting, San Francisco, California, USA, April 1997), pp. 397-402, 1997.
  103. Tutorial: T.-J. King and B. Gnade, “Flat panel display materials and large-area processing,” given at the MRS 1997 Spring Meeting (San Francisco, California, USA), March 1997.
  104. Invited Paper: T.-J. King, “Status and prospect of silicon-germanium TFT technology for AMLCD application,” Conference Record of the 1997 International Display Research Conference, pp. M29-M35, 1997.
  105. Invited Paper: T.-J. King, “Polycrystalline silicon thin films for active-matrix flat-panel displays,” presented at the 44th National Symposium of the American Vacuum Society (San Francisco, California, USA), October 1997.
  106. Invited Paper: T.-J. King and Y.-J. Tung, “Low-temperature poly-Si TFT technology for lightweight, high-performance displays,” Proceedings of the 1997 International Semiconductor Device Research Symposium (Charlottesville, Virginia, USA), pp. 451-454, 1997.
  107. Tutorial: T.-J. King and B. Gnade, “Flat panel display materials and large-area processing,” given at the MRS 1998 Spring Meeting (San Francisco, California, USA), April 1998.
  108. Invited Paper: S. Yamamichi, A. Yamamichi, D. Park, H. Yabuta, T. Iizuka, K. Arita, S. Sone, Y. Kato, S. Nishimoto, T.-J. King, C. Hu and M. Yoshida, “Reliability study on high dielectric constant (Ba,Sr)TiO3 thin film,” presented at the 193rd ECS Meeting (San Diego, California, USA), May 1998.
  109. Y. Lee, R. A. Gough, T.-J. King, Q. Ji, K. N. Leung, R. A. McGill, V. V. Ngo, M. D. Williams and N. Zahir, “Maskless ion beam lithography system,” presented at Micro- and Nano-Engineering ‘98 (Leuven, Belgium), September 1998.
  110. Invited Paper: T.-J. King, “Advanced gate technology for sub-0.25 micron CMOSFETs,” presented at the SPIE 1998 Symposium on Microelectronic Manufacturing (Santa Clara, California, USA), September 1998.
  111. Invited Paper: T.-J. King, “LSI on glass substrates,” presented at LCD/PDP International ‘98 (Tokyo, Japan), October 1998.
  112. Invited Paper: P. G. Carey, P. M. Smith, S. D. Theiss, P. Wickboldt, T. W. Sigmon, Y.-J. Tung and T.-J. King, “Poly-Si thin film transistors fabricated on plastic substrates,” 11th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Conference Proceedings, pp. 126-127, 1998.
  113. H. Takeuchi and T.-J. King, “Poly-Si1-xGex process integration for low sheet resistance gate CMOS technology,” Advances in Rapid Thermal Processing. Proceedings of the Symposium (Seattle, Washington, USA), Electrochemical Society Proceeding Vol. 99-10, pp. 277-284, 1999.
  114. Y. Lee, R. A. Gough, T.-J. King, Q. Ji and K.-N. Leung, “Maskless ion beam lithography system,” Microelectronic Engineering, Vol. 46, pp. 469-472, May 1999.
  115. Q. Ji, T.-J. King, Y. Y. Lee and K.-N. Leung, “Compact column design for a focused ion beam lithography system,” Proceedings of the SPIE, Vol. 3777, pp. 175-182, 1999.
  116. Invited Paper: T.-J. King, “Device design considerations for sub-50 nm CMOS,” Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials (Tokyo, Japan), pp. 28-29, 1999.
  117. P. Ranade, Y.-C. Yeo, Q. Lu, H. Takeuchi, T.-J. King and C. Hu, “Molybdenum as a gate electrode for deep sub-micron CMOS technology,” presented at the MRS 2000 Spring Meeting (San Francisco, California, USA), April 2000.
  118. J. Kedzierski, P. Xuan, V. Subramanian, E. Anderson, J. Bokor, T.-J. King and C. Hu, “A 20 nm Gate-Length Ultra-Thin Body p-MOSFET with Silicide Source/Drain,” Superlattices and Microstructures, Vol. 28, pp. 445-452, 2000. (Presented at the Silicon Nanoelectronics Workshop, Honolulu, Hawaii, USA, June 2000).
  119. Invited Talk: T.-J. King, "Thin-film transistor technologies for flexible, lightweight flat-panel displays," presented at the Association of Super-Advanced Electronics Technologies (ASET) International Forum on Low Power Displays (Tokyo, Japan), July 21, 2000.
  120. Invited Paper: T.-J. King, "Poly-Si TFT technologies for future flat-panel displays," Conference Record of the 20th International Display Research Conference (Palm Beach, Florida, USA), pp. 406-410, 2000.
  121. Y.-J. Tung, P. G. Carey, P. M. Smith, S. D. Theiss, P. Wickboldt, X. Meng, R. E. Weiss, G. A. Davis, V. W. Aebi and T.-J. King, "Polycrystalline silicon thin-film transistor technology for flexible large-area electronics," Proceedings of SPIE, Vol. 4295: Flat Panel Display Technology and Display Metrology II, Paper 4295A-15, 2001.
  122. Invited Talk: T.-J. King, "Ultra-scaled MOSFETs for future nanoelectronics," presented at The First Korea-U.S.-Japan Workshop on Nanostructure Science and Technology (Seoul, Korea), April 2001.
  123. Invited Talk: T.-J. King, "Materials Requirements for Future Thin-Body SOI CMOSFETs," presented at the MRS 2001 Fall Meeting, Symposium A: Materials Issues in Novel Si-Based Technology (Boston, Massachussetts, USA), November 2001.
  124. Invited Paper: P. Ranade, Q. Lu, I. Polishchuk, H. Takeuchi, C. Hu and T.-J. King, "Dual work function metal gate technology for future CMOS devices," presented at the 3rd International AVS Conference on Microelectronics and Interfaces (ICMI’02) (Santa Clara, California, USA), February 2002.
  125. Invited Paper: R. T. Howe and T.-J. King, "Low temperature LPCVD MEMS technologies," presented at the MRS 2002 Spring Meeting (San Francisco, California, USA), April 2002.
  126. Invited Paper: T.-J. King and R. T. Howe, "Interconnect issues for MEMS technology," presented at the Advanced Metallization Conference (San Diego, California, USA), October 2002.
  127. H. Takeuchi and T.-J. King, “Investigation of Interface Properties of CVD HfO2 by SCA (Surface Charge Analysis),” presented at the International SEMATECH Gate Stack Engineering Working Group Symposium (Austin, Texas, USA), October 16, 2002.
  128. Invited Paper: T.-J. King, "Gate material issues for high-k gate stacks," presented at the 33rd IEEE Interface Specialists Conference (San Diego, California, USA), December 2002.
  129. Invited Paper: T.-J. King, R. T. Howe and S. Sedky "Recent progress in modularly integrated MEMS technologies," International Electron Devices Meeting Technical Digest, pp. 199-202, 2002.
  130. Invited Paper: T.-J. King "Advanced materials and processes for nanometer-scale FinFETs," Proceedings of the International Electron Devices and Materials Symposia (Taipei, Taiwan, R. O. C.), pp. 11-15, 2002.
  131. Invited Paper: P. Ranade, Y.-K. Choi, D. Ha, H. Takeuchi and T.-J. King, "Metal gate technology for fully depleted SOI CMOS," to be presented at the 4th International AVS Conference on Microelectronics and Interfaces -- ICMI’03 (Santa Clara, California, USA), March 2003.
  132. Keynote (Plenary) Paper: T.-J. King "Opportunities and Challenges for Silicon-Based Nanotechnology," to be presented at the 2003 IEEE University/Government/Industry Microelectronics Symposium (Boise, Idaho, USA), June 2003.
last updated 12/26/02