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Background Readings
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Architecture
On-chip Network
- Benini L, De Micheli G. Powering
networks on chips [Conference Paper] International Symposium on System
Synthesis (IEEE Cat. No.01EX526). ACM. 2001, pp.33-8. New York, NY, US
- Luca Benini and Giovanni
De Micheli. Networks on Chip: A New SoC Paradigm
IEEE Computer, January 2002
- Ye TT, Benini L, De
Micheli G. Packetized on-chip interconnect communication
analysis for MPSoC 6th Design Automation and Test in Europe (DATE
03). Munich, Germany
(BibTex)
- Dally WJ. Towles B.
Route packets, not wires: on-chip interconnection
networks Proceedings 2001. 38th Design Automation Conference. Las
Vegas, NV, USA. 18-22 June 2001
(BibTex)
Errors
- Johnston A. Scaling and Technology
Issues for Soft Error Rates [Conference Paper] Proceedings 4th Annual
Research Conference on Reliability, Stanford University, October 2000
- Hentschke R, Marques F, Lima F, Carro L, Susin A, Reis R. Analyzing
area and performance penalty of protecting different digital modules with
Hamming code and triple modular redundancy [Conference Paper] Proceedings
15th Symposium on Integrated Circuits and Systems Design. IEEE Comput. Soc.
2002, pp.95-100. Los Alamitos, CA, USA
- Lin Li, N. Vijaykrishnan,
M. Kandemir and M. J. Irwin. Adaptive Error Protection for Energy Efficiency
2003 International Conference on Computer Aided Design (ICCAD'03)
(BibTex)
- Hegde R, Shanbhag NR.
Toward achieving energy efficiency in presence
of deep submicron noise IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol.8, no.4, Aug. 2000, pp.379-91 (BibTex)
Power/Energy
- Q. Wu, P. Juang, M. Martonosi, and D. Clark. Formal
online methods for voltage/frequency control in multiple clock domain microprocessors
Proceedings of the 11th International Conference on Architectural Support
for Programming Languages and Operating Systems (ASPLOS'04), October 7-13,
2004, Boston, Massachusetts, USA
- Brodersen RW, Horowitz MA, Markovic D, Nikolic B, Stojanovic V. Methods
for true power minimization IEEE/ACM International Conference on
Computer Aided Design. IEEE/ACM Digest of Technical Papers (Cat. No.02CH37391).
IEEE. 2002, pp.35-42. Piscataway, NJ, USA
- Meindl JD, Davis JA. The fundamental
limit on binary switching energy for terascale integration (TSI) [Journal
Paper] IEEE Journal of Solid-State Circuits, vol.35, no.10, Oct. 2000,
pp.1515-16. Publisher: IEEE, USA
- Dake Liu, Svensson
C. Power consumption estimation in CMOS VLSI
chips IEEE Journal of Solid-State Circuits, vol.29, no.6, June 1994,
pp.663-70. USA
- Raghunathan V, Srivastava
MB, Gupta RK. A survey of techniques for energy efficient
on-chip communication Proceedings 2003. Design Automation Conference
(IEEE Cat. No.03CH37451). IEEE. 2003, pp.900-5. Piscataway, NJ, USA
(BibTex)
Interconnect
- Li Shang, Li-Shiuan Peh and Niraj K. Jha, Power-Efficient
Interconnection Networks: Dynamic Voltage Scaling with Links Computer
Architecture Letters, Volume 1, No. 2, May 2002, pp. 1-4
- Krishnan R. de Gyvez JP. Veendrick HJM. Encoded-low swing technique
for ultra low power interconnect International Conference on Field-Programmable
Logic. Lisbon, Portugal. 1-3 Sept. 2003
- H. Zhang, V. George, and J. Rabaey. Low-Swing
On-Chip Signaling Techniques: Effectiveness and Robustness IEEE Transactions
on Very Large Scale Integration (Vlsi) Systems, vol.8, no.3, June 2000,
pp.264-72. USA
- M. Horowitz, C.-K.
K. Yang, S. Sidiropoulos. High-speed electrical signaling: overview
and limitations IEEE Micro, January 1998, pages 12-24 (BibTex)
- R. Ho, K. W. Mai and
M. A. Horowitz. The Future of Wires Proceedings
of the IEEE, April 2001, pages 490-504 (BibTex)
- Li Shang, Li-Shiuan
Peh and Niraj K. Jha. Dynamic Voltage Scaling with Links for Power
Optimization of Interconnection Networks Proceedings of the 9th International
Symposium on High-Performance Computer Architecture (HPCA), Anaheim, CA,
January 2003
(BibTex)
- Frederic Worm, Paolo
Ienne, Patric Thiran, Giovanni De Micheli. An Adaptive Low Power Transmission Scheme
for On-chip Networks International System Synthesis Symposium, October
2002 (BibTex)
- D. Bertozzi, L. Benini
and G. De Micheli. Low Power Error Resilient Encoding
for On-chip Data Buses DATE - International Conference on Design
and Test Europe, 2002
(BibTex)
- Nir Magen and Avinoam
Kolodny and Uri Weiser and Nachum Shamir Interconnect-Power Dissipation in a Microprocessor
Proceedings of the 2004 International Workshop on System Level Interconnect
Prediction (SLIP'04), Paris, France (BibTex)
Emerging
- Boon-Keat Tan, Yoshimura
R, Matsuoka T, Taniguchi K. An efficient data transmission interface for VLSI
systems using code-division multiple access technique ESSCIRC 2001.
Proceedings of the 27th European Solid-State Circuits Conference. Frontier
Group. 2001, pp.176-9. Paris, France
- Yoshimura R, Tan Boon
Keat, Ogawa T, Hatanaka S, Matsuoka T, Taniguchi K. DS-CDMA
wired bus with simple interconnection topology for parallel processing system
LSIs 2000 IEEE International Solid-State Circuits Conference. Digest
of Technical Papers (Cat. No.00CH37056). IEEE. 2000, pp.370-1. Piscataway,
NJ, USA
- Chang, M.F.; Roychowdhury,
V.P.; Liyang Zhang; Hyunchol Shin; Yongxi Qian. RF/wireless interconnect for inter-
and intra-chip communications Proceedings of the IEEE, Vol.89, Iss.4,
Apr 2001, Pages:456-466