I

Research

Current:

Dense Network Architecture for Storage

With the advances both in technology and hardware integration, sensor node is now increasingly shrinking in size while at the same time attain higher capabilities such as storage capacity. At the same time, advances in communication technology has made it possible to build a dense network with potentially millions of nodes while minimizing communication power. In this work, we study the feasibility of a storage architecture in such dense network. We looked at issues ranging from data durability, routing scalability and availibility of data under churn. This work borrow heavily from existing work on distributed hash-table at Internet-scale and scalable routing protocols from sensor network domain.

Presentations

pentium 4 Prescott core
The newest Intel Pentium 4 (Prescott core) consumes a worst case power of 89-103W. Part of this power can be reduced by reducing transition activities.

Past:

Low Power Interconnect

Scaling trends have continually increased the importance of wires relative to logic. Among other things, the ever rising ambitions of computer architects have caused wire lengths to remain constant or increase -- even as transistor sizes have shrunk. This observation suggests that energy conscious designers should focus some of their attention on the energy dissipated by on-chip wires. Clearly, this process can involve a variety of techniques at the level of technology, circuits, and architectures.

In this endeavor, we exploit abundant transistors to transform information into a form that is less expensive to communicate; our techniques are complementary to other options such as reducing voltage swing. Energy is consumed when wires change state. Thus, our goal will be to eliminate or reduce the total number of wire transitions while also reducing cross-coupling energy. Compression techniques have long been used to reduce the volume of off-chip communication. Given the large capacitances of cross-chip interconnects, compression circuits can easily save more power than they utilize. In contrast, we address a more difficult question: Is it possible to reduce the traffic over on-chip buses and save energy while doing so?. Since on-chip wires have capacitances that are orders-of-magnitude smaller than cross-chip interconnects, the answer to this question requires careful accounting of the energy consumed by the encoding and decoding process.