In the software-based design methodologies for embedded systems, systems are designed and programmed in a functional computation model. This can be finite state machines, data flow networks, Petri nets, Descrte events, etc., depending on the target application. Software synthesis techniques are used to derive implementation code, like C, from these models. We are interested in the finites state machine model, derived from high-level language Esterel. Currently, the automatically generated code is not competitive in terms of execution speed, because the control portion (up to 90%) runs slow on normal ALU-based architectures.
This project studies an architecture platform (possibly reconfigurable), where a coprocessor is dedicated for executing the control portion of the code. One idea is to use FPGA to configure and execute the control code. Another idea is to use memory to load blocks of control functions and evaluate the output (ref[1]). The key, in general, is the interface between the ALU and the coprocessor.
We would use MVSIS (ref[2]) to generate C code from Esterel, and use a specialized version of compiler/profiler gcc to simulate/profile the performance of the proposed architecture.