Offical Computer Architecture Preliminary Exam Syllabus

http://www.cs.berkeley.edu/~yatish/prelim/intel.txt

6/12/02

  1. Sarita Adve and Mark Hill, "Weak Ordering -- A New Definition" [CITESEER]
  2. Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop Gupta, and John Hennessy, "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors," Proceedings of the International symposium on Computer Architecture, 1990. [PS]
  3. Wei C. Yen, David W.L. Yen, and King-Sun Fu, "Data Coherence Problem in a Multicache System," IEEE Transactions on Computers, Vol c-34 No. 1, January 1985.
  4. Mark D. Hill, "Multiprocessors Should Support Simple Memory-Consistency Models," [IEEE]
  5. David Chaiken, John Kubatowicz, and Anant Agarwal, "LimitLESS Directories: A Scalable Cache Coherence Scheme." [CITESEER]

06/19/02

  1. [PS] Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, and John Hennessy, "The DASH Prototype: Implementation and Performance,"
  2. [CITESEER] Noakes, Michael D. and Wallach, Deborah A. and Dally, William J. "The J-Machine Multicomputer: An Architectural Evaluation,
  3. [CITESEER]Steven Reinhardt, James Larus, and David Wood, "Tempest and Typhoon: User-Level Shared Memory,"
  4. [CITESEER] Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, and Donald Yeung, "The MIT Alewife Machine: Architecture and Performance,"
  5. [PS] Jeffrey Kuskin, et al. "The Stanford FLASH Multiprocessor"
  6. [PS] Stefanos N. Damianakis, Angelos Bilas, Cezary Dubnicki, and Edward W. Felten, "Client-Server Computing on the SHRIMP Multicomputer." IEEE Micro 17(1):8-18, February 1997.

07/08/02

  1. [ACM] D. A. Patterson, G. A. Gibson, R. H. Katz, "The Case for Redundant Arrays of Inexpensive Disks (RAID)", Proceedings ACM SIGMOD Conference, Chicago, IL, (May 1988).
  2. [CITESEER] Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, and Klaus Erik Schauser, "Active Messages: a Mechanism for integrated Communication and Computation,"
  3. [CITESEER] Kenneth Mackenzie, John Kubiatowicz, Anant Agarwal, and Frans Kaashoek. "Exploiting Two-Case Delivery for Fast Protected Messaging."
  4. [CITESEER] Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and David A. Wood, "Coherent Network Interfaces for Fine-Grain Communication."
  5. [CITESEER] Dally, William J., "Performance Analysis of k-ary n-cube Interconnection Networks,"
  6. [PDF]Patterson, D. A., A. Brown, P. Broadwell, G. Candea, M. Chen, J. Cutler, P. Enriquez, A. Fox, E. Kiciman, M. Merzbacher, D. Oppenheimer, N. Sastry, W. Tetzlaff, J. Traupman, N. Treuhaft. Recovery-Oriented Computing (ROC): Motivation, Definition, Techniques, and Case Studies. UC Berkeley Computer Science Technical Report UCB//CSD-02-1175, March 15, 2002.
  7. [PDF] Oppenheimer, D., A. Brown, J. Beck, D. Hettena, J. Kuroda, N. Treuhaft, D.A. Patterson, and K. Yelick. ROC-1: Hardware Support for Recovery-Oriented Computing. IEEE Transactions on Computers, vol. 51, no. 2, February 2002.

  1. David Patterson and David Ditzel, "The Case for the Reduced Instruction Set Computer," [PDF]
  2. Anoop Gupta, John Hennessy, Kourosh Gharachorloo, todd Mowry, and Wolf-Dietrich Weber, "Comparative Evaluation of Latency Reducing and tolerating Techniques",
  3. Douglas Clark and William Strecker, "Comments on 'The Case for the Reduced instruction Set Computer' by Patterson and Ditzel" [PDF]
  4. *Diefendorff, "Transistor Budgets Go Ballistic" [PDF]
  5. James Smith and Andrew Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors" [ACM]

  1. David Patterson and Carlo Sequin, "RISC I: A Reduced Instruction Set VLSI Computer" [ACM]
  2. Richard Russel, "The CRAY-1 Computer System", Communications of the ACM, 21(1) 63-72, January 1978 [ACM]
  3. G. Amdahl, G. Blaauw, F. Brooks, Jr., "Architecture of the IBM System/360", IBM Journal, April 1964 [PDF]
  4. J.E. Thornton, "Parallel Operation in the Control Data 6600"
  5. David Ditzel and David Patterson, "Retrospective on High-Level Computer Architecture"

  1. Gregory Papadopoulos and David Culler, "Monsoon: an Explicit Token-Store Architecture"
  2. Jack Dennis and David Misunas, "A Preliminary Architecture for a Basic Data-Flow Processor"
  3. David Moon, "Symbolics Architecture", IEEE Computer, 1987
  4. Gurindar Sohi and Sriram Vajapeyam, "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors",

  1. R. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic units"
  2. E. Hauck and B. Dent, "Burroughs' B6500/B7500 stack Mechanism," AFIP SJCC, 1968
  3. Wen-mei Hwu and Yale Patt, "HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality," [PDF]
  4. James Smith, "Decoupled Access/Execute Computer Architectures" [PDF]
  5. Joseph Fisher, "Very Long Instruction Word Architectures and the ELI-512", [PDF]
  6. Michael Smith, Mark horowitz, and Monica Lam, "Efficient Superscalar performance Through Boosting", [PDF]
  7. Robert Colwell, Robert Nix, John O'Donnel, David Papworth, and Paul Rodman, "A VLIW Architecture for a Trace Scheduling Compiler", [PDF]

  1. [ACM] Subbarao Palacharla, Norman P. Jouppi and J. E. Smith , "Complexity Efficient Superscalar Processors"
  2. M. Franklin and G. S. Sohi, "The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,"
  3. E. Rotenberg, Q. Jacobson, Y. Sazeides, and J. Smith, "Trace Processors",
  4. Cliff Young and Michael D. Smith. "Improving the Accuracy of Static Branch Prediction Using Branch Correlation,"
  5. Andreas Moshovos, Scott E. Breach, T.N. Vijaykumar, and Gurindar S. Sohi, "Dynamic Speculation and Synchronization of Data Dependences",

  1. Dean Tullsen, Susan Eggers, Henry Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism",
  2. Tse-Yu Yeh and Yale Patt, "Alternative Implementations of Two-level Adaptive Branch Prediction",
  3. Cliff Young, Nicolas Gloy, and Michael D. Smith, "A Comparative Analysis of Schemes for Correlated Branch Prediction",
  4. *Marius Evers, Sanjay J. Patel, Robert S. Chappell, and Yale N. Patt, "Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work,"

  1. *Chih-Chieh Lee, I-Cheng Chen, and Trevor Mudge, The Bi-Mode Branch Predictor
  2. George Z. Chrysos and Joel S. Emer, "Memory Dependence Prediction using Store Sets",
  3. *Mikko H. Lipasti, Christopher B. Wilkerson and John Paul Shen, Value locality and load value prediction
  4. Avinash Sodani and Gurindar S. Sohi, "Dynamic Instruction Reuse",

11/16/01

  1. *Yiannakis Sazeides and James E. Smith, The Predictability of Data Values,
  2. *Brad Calder, Glenn Reinman, and Dean Tullsen, Selective Value Prediction
  3. *Joel Emer and Nikolas Gloy, "A Language for Describing Predictors and its Application to Automatic Synthesis"
  4. Keith Farkas, Paul Chow, Norman Jouppi, and Zvonko Vranesic, "Memory-System Design Considerations for Dynamically-Scheduled Processors",

11/23/01

  1. Dirk Grunwald and Artur Klauser, "Confidence Estimation for Speculation Control",
  2. David Kroft, "Lockup-Free Instruction Fetch/Prefetch Cache Organization",
  3. Normal Jouppi, "Improving Direct-mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch buffers".

11/30/01

  1. Todd Mowry, Monica Lam, and Anoop Gupta, "Design and Evaluation of a Compiler Algorithm for Prefetching,
  2. Subbarao Palacharla and R.E. Kessler, "Evaluating Stream Buffers as a Secondary Cache Replacement",
  3. B. Ramakrishna Rau, "Pseudo-Randomly Interleaved Memory",

12/7/01

  1. *Todd M. Austin, DIVA: a reliable substrate for deep submicron microarchitecture design,
  2. *Steven K. Reinhardt and Shubhendu S. Mukherjeem, Transient fault detection via simultaneous multithreading,

12/14/01

  1. M. Y. Hsiao, "A Class of Optimal Minimum Odd-weight-column SC-DED Codes",
  2. Shigeo Kaneda, "A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications",
  3. *M. Blaum, J. Brady, J. Bruck and J. Menon, EVENODD: an optimal scheme for tolerating double disk failures in RAID architectures
  4. *David patterson, Garth Gibson, and Randy Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID)

12/21/01

  1. Mackenzie, and Donald Yeung, "The MIT Alewife Machine: Architecture and Performance,"
  2. *Anant Agarwal, Richard Simoni, John Hennessy, and Mark Horowitz, An Evaluation of Directory Schemes for Cache Coherence,
  3. *Chris Gniady, Babak Falsafi, and T.N. Vijaykumar, Is SC + ILP = RC?,

Papers on Cache Coherence: Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop Gupta, and John Hennessy, "Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors,"

Papers on Experimental Parallel Machines:

General Networking:

  1. Chapter 7 of "Computer Architecture: a Quantitative Approach, Second Edition" by Hennessy and Patterson contains some discussion of networking.
  2. An understanding of TCP/IP and similar protocol issues can be gained from Internetworking with TCP/IP, Second Edition, by D.E. Comer.
  3. In addition, Parallel Computer Architecture: A Hardware/Software Approach by David E. Culler and Jaswinder Pal Singh contains material on networking for parallel processors.

Network Router Design/Deadlock Avoidance:

  1. D.W. Dobberpuhl, et al, "A 200-MHz 64-b Dual-Issue CMOS Microprocessor,"
  2. J. Montanaro, et. al, "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor,"

Network Interface Design: