Test case 8: Available events and hardware information.
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Vendor string and code   : IBM (-1)
Model string and code    : POWER3-II (128)
CPU revision             : 524288.000000
CPU Megahertz            : 375.000000
CPU's in an SMP node     : 16
Nodes in the system      : 1
Total CPU's in the system: 16
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Name		Code		Avail	Deriv	Description (Note)
PAPI_L1_DCM	0x80000000	Yes	Yes	Level 1 data cache misses (PM_LD_MISS_L1,PM_ST_MISS)
PAPI_L1_ICM	0x80000001	Yes	No	Level 1 instruction cache misses (PM_IC_MISS)
PAPI_L2_DCM	0x80000002	No	No	Level 2 data cache misses ()
PAPI_L2_ICM	0x80000003	No	No	Level 2 instruction cache misses ()
PAPI_L3_DCM	0x80000004	No	No	Level 3 data cache misses ()
PAPI_L3_ICM	0x80000005	No	No	Level 3 instruction cache misses ()
PAPI_L1_TCM	0x80000006	Yes	Yes	Level 1 cache misses (PM_IC_MISS,PM_LD_MISS_L1,PM_ST_MISS)
PAPI_L2_TCM	0x80000007	No	No	Level 2 cache misses ()
PAPI_L3_TCM	0x80000008	No	No	Level 3 cache misses ()
PAPI_CA_SNP	0x80000009	Yes	No	Requests for a snoop (PM_SNOOP)
PAPI_CA_SHR	0x8000000a	Yes	No	Requests for exclusive access to shared cache line (PM_SNOOP_E_TO_S)
PAPI_CA_CLN	0x8000000b	No	No	Requests for exclusive access to clean cache line ()
PAPI_CA_INV	0x8000000c	No	No	Requests for cache line invalidation ()
PAPI_CA_ITV	0x8000000d	Yes	No	Requests for cache line intervention (PM_SNOOP_PUSH_INT)
PAPI_L3_LDM	0x8000000e	No	No	Level 3 load misses ()
PAPI_L3_STM	0x8000000f	No	No	Level 3 store misses ()
PAPI_BRU_IDL	0x80000010	Yes	No	Cycles branch units are idle (PM_BRU_IDLE)
PAPI_FXU_IDL	0x80000011	Yes	No	Cycles integer units are idle (PM_FXU_IDLE)
PAPI_FPU_IDL	0x80000012	Yes	No	Cycles floating point units are idle (PM_FPU_IDLE)
PAPI_LSU_IDL	0x80000013	Yes	No	Cycles load/store units are idle (PM_LSU_IDLE)
PAPI_TLB_DM	0x80000014	No	No	Data translation lookaside buffer misses ()
PAPI_TLB_IM	0x80000015	No	No	Instruction translation lookaside buffer misses ()
PAPI_TLB_TL	0x80000016	Yes	No	Total translation lookaside buffer misses (PM_TLB_MISS)
PAPI_L1_LDM	0x80000017	Yes	No	Level 1 load misses (PM_LD_MISS_L1)
PAPI_L1_STM	0x80000018	Yes	No	Level 1 store misses (PM_ST_MISS)
PAPI_L2_LDM	0x80000019	Yes	No	Level 2 load misses (PM_LD_MISS_EXCEED_L2)
PAPI_L2_STM	0x8000001a	Yes	No	Level 2 store misses (PM_ST_MISS_EXCEED_L2)
PAPI_BTAC_M	0x8000001b	Yes	No	Branch target address cache misses (PM_BTAC_MISS)
PAPI_PRF_DM	0x8000001c	Yes	No	Data prefetch cache misses (PM_PREF_MATCH_DEM_MISS)
PAPI_L3_DCH	0x8000001d	No	No	Level 3 Data Cache Hits ()
PAPI_TLB_SD	0x8000001e	Yes	No	Translation lookaside buffer shootdowns (PM_TLBSYNC_RERUN)
PAPI_CSR_FAL	0x8000001f	Yes	No	Failed store conditional instructions (PM_RESRV_CMPL)
PAPI_CSR_SUC	0x80000020	Yes	No	Successful store conditional instructions (PM_ST_COND_FAIL)
PAPI_CSR_TOT	0x80000021	Yes	No	Total store conditional instructions (PM_RESRV_RQ)
PAPI_MEM_SCY	0x80000022	Yes	Yes	Cycles Stalled Waiting for memory accesses (PM_CMPLU_WT_LD,PM_CMPLU_WT_ST)
PAPI_MEM_RCY	0x80000023	Yes	No	Cycles Stalled Waiting for memory Reads (PM_CMPLU_WT_LD)
PAPI_MEM_WCY	0x80000024	Yes	No	Cycles Stalled Waiting for memory writes (PM_CMPLU_WT_ST)
PAPI_STL_ICY	0x80000025	Yes	No	Cycles with no instruction issue (PM_0INST_DISP)
PAPI_FUL_ICY	0x80000026	No	No	Cycles with maximum instruction issue ()
PAPI_STL_CCY	0x80000027	Yes	No	Cycles with no instructions completed (PM_0INST_CMPL)
PAPI_FUL_CCY	0x80000028	No	No	Cycles with maximum instructions completed ()
PAPI_HW_INT	0x80000029	No	No	Hardware interrupts ()
PAPI_BR_UCN	0x8000002a	No	No	Unconditional branch instructions ()
PAPI_BR_CN	0x8000002b	Yes	No	Conditional branch instructions (PM_CBR_DISP)
PAPI_BR_TKN	0x8000002c	No	No	Conditional branch instructions taken ()
PAPI_BR_NTK	0x8000002d	No	No	Conditional branch instructions not taken ()
PAPI_BR_MSP	0x8000002e	Yes	No	Conditional branch instructions mispredicted (PM_MPRED_BR_CAUSED_GC)
PAPI_BR_PRC	0x8000002f	Yes	No	Conditional branch instructions correctly predicted (PM_BR_PRED)
PAPI_FMA_INS	0x80000030	Yes	No	FMA instructions completed (PM_EXEC_FMA)
PAPI_TOT_IIS	0x80000031	Yes	No	Instructions issued (PM_INST_DISP)
PAPI_TOT_INS	0x80000032	Yes	No	Instructions completed (PM_INST_CMPL)
PAPI_INT_INS	0x80000033	Yes	Yes	Integer instructions (PM_FXU0_PROD_RESULT,PM_FXU1_PROD_RESULT,PM_FXU2_PROD_RESULT)
PAPI_FP_INS	0x80000034	Yes	Yes	Floating point instructions (PM_FPU0_CMPL,PM_FPU1_CMPL)
PAPI_LD_INS	0x80000035	Yes	No	Load instructions (PM_LD_CMPL)
PAPI_SR_INS	0x80000036	Yes	No	Store instructions (PM_ST_CMPL)
PAPI_BR_INS	0x80000037	Yes	No	Branch instructions (PM_BR_CMPL)
PAPI_VEC_INS	0x80000038	No	No	Vector/SIMD instructions ()
PAPI_FLOPS	0x80000039	Yes	Yes	Floating point instructions per second (PM_CYC,PM_FPU0_CMPL,PM_FPU1_CMPL)
PAPI_RES_STL	0x8000003a	No	No	Cycles stalled on any resource ()
PAPI_FP_STAL	0x8000003b	No	No	Cycles the FP unit(s) are stalled ()
PAPI_TOT_CYC	0x8000003c	Yes	No	Total cycles (PM_CYC)
PAPI_IPS	0x8000003d	Yes	Yes	Instructions per second (PM_CYC,PM_INST_CMPL)
PAPI_LST_INS	0x8000003e	Yes	Yes	Load/store instructions completed (PM_LD_CMPL,PM_ST_CMPL)
PAPI_SYC_INS	0x8000003f	Yes	No	Synchronization instructions completed (PM_SYNC)
PAPI_L1_DCH	0x80000040	No	No	L1 data cache hits ()
PAPI_L2_DCH	0x80000041	No	No	L2 data cache hits ()
PAPI_L1_DCA	0x80000042	No	No	L1 data cache accesses ()
PAPI_L2_DCA	0x80000043	No	No	L2 data cache accesses ()
PAPI_L3_DCA	0x80000044	No	No	L3 data cache accesses ()
PAPI_L1_DCR	0x80000045	No	No	L1 data cache reads ()
PAPI_L2_DCR	0x80000046	No	No	L2 data cache reads ()
PAPI_L3_DCR	0x80000047	No	No	L3 data cache reads ()
PAPI_L1_DCW	0x80000048	No	No	L1 data cache writes ()
PAPI_L2_DCW	0x80000049	No	No	L2 data cache writes ()
PAPI_L3_DCW	0x8000004a	No	No	L3 data cache writes ()
PAPI_L1_ICH	0x8000004b	No	No	L1 instruction cache hits ()
PAPI_L2_ICH	0x8000004c	No	No	L2 instruction cache hits ()
PAPI_L3_ICH	0x8000004d	No	No	L3 instruction cache hits ()
PAPI_L1_ICA	0x8000004e	No	No	L1 instruction cache accesses ()
PAPI_L2_ICA	0x8000004f	No	No	L2 instruction cache accesses ()
PAPI_L3_ICA	0x80000050	No	No	L3 instruction cache accesses ()
PAPI_L1_ICR	0x80000051	No	No	L1 instruction cache reads ()
PAPI_L2_ICR	0x80000052	No	No	L2 instruction cache reads ()
PAPI_L3_ICR	0x80000053	No	No	L3 instruction cache reads ()
PAPI_L1_ICW	0x80000054	No	No	L1 instruction cache writes ()
PAPI_L2_ICW	0x80000055	No	No	L2 instruction cache writes ()
PAPI_L3_ICW	0x80000056	No	No	L3 instruction cache writes ()
PAPI_L1_TCH	0x80000057	No	No	L1 total cache hits ()
PAPI_L2_TCH	0x80000058	No	No	L2 total cache hits ()
PAPI_L3_TCH	0x80000059	No	No	L3 total cache hits ()
PAPI_L1_TCA	0x8000005a	No	No	L1 total cache accesses ()
PAPI_L2_TCA	0x8000005b	No	No	L2 total cache accesses ()
PAPI_L3_TCA	0x8000005c	No	No	L3 total cache accesses ()
PAPI_L1_TCR	0x8000005d	No	No	L1 total cache reads ()
PAPI_L2_TCR	0x8000005e	No	No	L2 total cache reads ()
PAPI_L3_TCR	0x8000005f	No	No	L3 total cache reads ()
PAPI_L1_TCW	0x80000060	No	No	L1 total cache writes ()
PAPI_L2_TCW	0x80000061	No	No	L2 total cache writes ()
PAPI_L3_TCW	0x80000062	No	No	L3 total cache writes ()
PAPI_FML_INS	0x80000063	No	No	Floating point multiply instructions ()
PAPI_FAD_INS	0x80000064	No	No	Floating point add instructions ()
PAPI_FDV_INS	0x80000065	Yes	No	Floating point divide instructions (PM_FPU_FDIV)
PAPI_FSQ_INS	0x80000066	Yes	No	Floating point square root instructions (PM_FPU_FSQRT)
PAPI_FNV_INS	0x80000067	No	No	Floating point inverse instructions ()
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Verification:
Check your architecture and substrate file