Yury Markovskiy

Graduate Student Researcher
University of California at Berkeley
Department of Electrical Engineering and Computer Sciences

441 Soda Hall
Berkeley, CA 94720
510-643-8229

Email: yurym AT cs DOT berkeley DOT edu

Research

Adviser: John Wawrzynek

High-level techniques for performance variability and fault tolerance on Network-on-Chip (PhD)

With reduction in transistor sizes and increases in parametric and functional variability, it is no longer be possible to manage die yields at design time. Designers employ a range of methods to ``over-engineer'' circuits, but this comes at the cost of wasted die area, power, and performance. Multi-core chips with network-on-chip (NoC) offer regularity in communication and computation blocks that opens the door to high-level architectural techniques to mitigate the effects of performance variability and faults, which can translate to an improvement in manufacturing yield.

Such techniques include core sparing and dynamic network routing. We demonstrate analytical yield and cost models for core sparing, a strategy of using only a subset of architected redundant cores. Core sparing offers asymptotic reduction in the total chip cost and is more efficient than circuit-level redundancy and fault-tolerance. Adaptive network routing is critical to enable core sparing. We show that adaptive routing additionally minimizes the impact of performance variability across the cores, instead of masking the problems by ``over-engineering.'' Thus by raising the level of abstraction, these high level architectural techniques (akin to OS resource management) provide a consistent, uniform way to deal with inter-/intra-die static and dynamic performance variations and faults.
  • Yury Markovsky, John Wawrzynek. "On the opportunity to improve system yield with multi-core architectures" in IEEE International Workshop on Design for Manufacturability and Yield (DFM&Y, Santa Clara, CA, October 2007). [PDF]
  • Yury Markovsky, John Wawrzynek. "Core sparing and dynamic routing for performance variability and fault tolerance" [PDF slides]

Quasi-Static Scheduling for SCORE (Masters)

The primary impediment to effective exploitation of reconfigurable devices (FPGAs) as computing devices is lack of automatic performance scaling and compatibility across device generations. SCORE project (part of BRASS) tackles this problem through resource virtualization and the accompanying programming and execution models to enable a scalable general purpose computing architecture for dynamic, run time reconfigurable devices.

Accommodating a range of interesting applications with dynamic behavior (such as multimedia coders) requires an expressive computational model and presents performance challenges in its run time support (OS). My work focuses on low-overhead scheduling for SCORE architecture, which employed a variant of Kahn Process Network (a network of FSMs extended with data-paths) as the computational model.
  • MS Report: Quasi-Static Scheduling for SCORE
  • Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, Andre DeHon and John Wawrzynek. ``Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine'' in Proc. of the Tenth ACM International Symposium on Field- Programmable Gate Arrays (FPGA 2002, Monterey, CA, Feb. 2002). [PDF]
  • Andre DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stelios Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek. ``Stream Computations Organized for Reconfigurable Execution'' in the Journal of Microprocessors and Microsystems 30 (2006) 334-354. [PDF]
  • Nicholas Weaver, Yury Markovskiy, Yatish Patel, and John Wawrzynek. ``Post Placement C-slow Retiming for the Xilinx Virtex FPGA'' in Proc. of the Eleventh ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2003, Monterey, CA, Feb. 2003). [PDF]

ZUMA and Ambient OS for Smart Home Environments

A modern home contains a wide range of disconnected communication networks, each with different functions and implementation architectures. The user experience as well as the overall functionality would be vastly enhanced if these networks could collaborate in a seamless fashion. Such collaboration requires disparate devices and components to interoperate in a user friendly, scalable and upgradeable fashion. We believe that such cooperation might be most efficiently enabled with the supporting infrastructure, The Universal Contents Router (UCR). The UCR moves the burden of connectivity away from the end devices to the system core.
  • J. van Greunen, Y. Markovsky, C. R. Baker, J. Rabaey, J. Wawrzynek, A. Wolisz. "A Platform for Smart Home Environments: The Case for Infrastructure" in Proc. of the 2nd International Conf. on Intelligent Environments (IE06, Athens, Greece, July 2006). [PDF]
  • C. R. Baker, Y. Markovsky, J. van Greunen, J. Rabaey, J. Wawrzynek, A. Wolisz. ``ZUMA: A Platform for Smart-Home Environments'' in Proc. of the 2nd International Conf. on Intelligent Environments (IE06, Athens, Greece, July 2006). [PDF]

Classes:

  • ''It has been said that democracy is the worst form of government except all the others that have been tried.'' -- Winston Churchill
  • ''A bookstore is one of the only pieces of evidence we have that people are still thinking.'' -- Jerry Seinfeld
  • ''In order to become the master, the politician poses as the servant.'' --Charles de Gaulle
  • ''Politics is the gentle art of getting votes from the poor and campaign funds from the rich, by promising to protect each from the other.'' --Oscar Ameringer
  • ''Politicians are like diapers. They both need changing regularly and for the same reason.'' --Anonymous
  • Politics: "Poli" a Latin word meaning "many"; and tics meaning "bloodsucking creatures." -- Robin Williams
  • ''The partisan, when he is engaged in a dispute, cares nothing about the rights of the question, but is anxious only to convince his hearers of his own assertions.'' -- Plato, Dialogues, Phaedo