04/07
LEON 3-slow interface  notes 

1. Understand the core configuration module, remove unnecessary parts (UART). --> Yury

2. We have crit part for the original core ~43ns ~23MHz.
   Default effort P&R

3. Triple:

   - pipeline regs - propagate context #   -->Yatish
   - control: PC, exception regs, etc.     -->Yatish

   - regfile x3                            --> Yury 
   - cache I, D, x3 in size (double clocking ?)  --> Yury

4. Find out how programs make it into cache to run benchmark simulations
   GCC for SPARC   --> Yatish